Journal ArticleDOI
A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions
TLDR
In this article, an analytical sub-threshold surface potential model for short-channel MOSFETs is presented, where the effect of varying depth of the channel depletion layer on the surface potential has been considered.Abstract:
An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.read more
Citations
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Journal ArticleDOI
A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile
TL;DR: In this paper, a two-dimensional model for the threshold voltage of the short-channel double-gate MOSFETs with a vertical Gaussian-like doping profile is proposed.
Journal ArticleDOI
Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model
TL;DR: In this article, the authors report a systematic, quantitative investigation of analog and RF performance of cylindrical surrounding-gate (SRG) silicon MOSFETs and derive a pseudo-two-dimensional (2D) approach applying Gauss's law in the channel region.
Journal ArticleDOI
1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model
TL;DR: An analytical pseudo-two-dimensional model for the transconductance generation factor of cylindrical surrounding gate (SRG) metal-oxide-semiconductor field effect transistor (MOSFET) and the obtained g m /I d model has been implemented in modelling the 1 /f low-frequency noise (LFN).
Journal ArticleDOI
An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects
TL;DR: An analytical sub-threshold model for surface potential and threshold voltage of a triple-material double-gate DG metal-oxide-semiconductor field effect transistor was developed by using a rectangular Gaussian box in the channel depletion region.
Journal ArticleDOI
A new analytical subthreshold model of SRG MOSFET with analogue performance investigation
TL;DR: In this article, a pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in sub-threshold regime is presented.
References
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Book
Operation and modeling of the MOS transistor
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
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Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
CMOS analog integrated circuits based on weak inversion operations
Eric A. Vittoz,J. Fellrath +1 more
TL;DR: In this paper, a simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications and verified experimentally for both p-and n-channel test transistors of a Si-gate low-voltage CMOS technology.
Journal ArticleDOI
Threshold voltage model for deep-submicrometer MOSFETs
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Journal ArticleDOI
Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's
TL;DR: The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement.