Journal ArticleDOI
Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs
Tor A. Fjeldly,Michael Shur +1 more
TLDR
An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the thresholdvoltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed as discussed by the authors.Abstract:
An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators. >read more
Citations
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Journal ArticleDOI
Introduction to flash memory
TL;DR: The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible and an insight into the multilevel approach, where two bits are stored in the same cell, is presented.
Journal ArticleDOI
Elementary scattering theory of the Si MOSFET
TL;DR: In this article, a simple one-flux scattering theory of the silicon MOSFET is introduced, where currentvoltage characteristics are expressed in terms of scattering parameters rather than a mobility.
Journal ArticleDOI
Power minimization in IC design: principles and applications
TL;DR: An in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems is presented and the many issues facing designers at architectural, logical, and physical levels of design abstraction are described.
Journal ArticleDOI
Power conscious CAD tools and methodologies: a perspective
Dharmesh Singh,Jan M. Rabaey,Massoud Pedram,Francky Catthoor,S. Rajgopal,Naresh Kumar Sehgal,Thomas J. Mozdzen +6 more
TL;DR: The CAD tools and methodologies required to effect efficient design for low power are described in the form of a tutorial and an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design.
Journal ArticleDOI
Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs
TL;DR: In this paper, a physically based model for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs has been derived based on an analytical solution of 2-D Poisson's equation (in cylinrical coordinates) in which the mobile charge term has been included.
References
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Journal ArticleDOI
A charge-sheet model of the MOSFET
TL;DR: In this paper, the authors compared the Pao-Sah double-integral model with the charge sheet model for long-channel MOSFETs and found that the charge-sheet model is simpler to extend to two or three dimensions.
Book
Physics of Semiconductor Devices
TL;DR: In this article, the authors present a review of the properties of Semiconductors and their properties in terms of physics and properties of devices, including the following: 1.1 Introduction. 1.2 Crystal Structure.
Journal ArticleDOI
A simple theory to predict the threshold voltage of short-channel IGFET's
TL;DR: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects in this paper, which is valid for short and long-channel lengths.
Journal ArticleDOI
VLSI limitations from drain-induced barrier lowering
TL;DR: In this paper, the important design parameters relating to Drain-Induced Barrier lowering (DIBL) are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results.