A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
Stefan Pechmann,Timo Mai,Matthias Volkel,Mamathamba Kalishettyhalli Mahadevaiah,Eduardo Perez,Emilio Perez-Bosch Quesada,Marc Reichenbach,Christian Wenger,Amelie Hagelauer +8 more
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The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.Abstract:
In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.read more
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A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows
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TL;DR: In this paper , the authors present a read circuit for RRAM cells based on voltage evaluation, which is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability.
Proceedings ArticleDOI
A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows
TL;DR: In this article , the authors present a read circuit for RRAM cells based on voltage evaluation, which is able to resolve very small resistance ratios of up to 1.31 while offering multi-level capability.
References
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Multilevel HfO2-based RRAM devices for low-power neuromorphic networks
Valerio Milo,Cristian Zambelli,Piero Olivo,Eduardo Perez,Mamathamba Kalishettyhalli Mahadevaiah,Oscar G. Ossorio,Ch. Wenger,Daniele Ielmini +7 more
TL;DR: This work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption by studying the material, device, and architecture aspects of resistive switching memory devices for implementing a 2-layer neural network for pattern recognition.
Proceedings ArticleDOI
A read-monitored write circuit for 1T1M multi-level memristor memories
Harika Manem,Garrett S. Rose +1 more
TL;DR: A sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit storage in each data cell (memristor), is proposed and the usage of the exponential drift Memristor model is used to further enhance write speeds of these devices which are otherwise much slower.
Journal ArticleDOI
Analysis of the statistics of device-to-device and cycle-to-cycle variability in TiN/Ti/Al:HfO2/TiN RRAMs
Eduardo Perez,D. Maldonado,Christian Acal,Juan Eloy Ruiz-Castro,F. J. Alonso,Ana M. Aguilera,Francisco Jiménez-Molinos,Ch. Wenger,Juan Bautista Roldán +8 more
TL;DR: In this article, an alternative approach based on phase-type distributions is proposed to model the forming, reset and set voltage distributions for Al:HfO2-based RRAM devices.
Journal ArticleDOI
Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention
Eduardo Perez,Cristian Zambelli,Mamathamba Kalishettyhalli Mahadevaiah,Piero Olivo,Christian Wenger +4 more
TL;DR: A multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels and introduces for the first time the proper combination of current compliance control and program/verify paradigms.
Journal ArticleDOI
A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays
TL;DR: In this paper, a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element is presented. But it is not suitable for use in the next-generation memory.