Journal ArticleDOI
An improved frequency compensation technique for CMOS operational amplifiers
Reads0
Chats0
TLDR
In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.Abstract:
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.read more
Citations
More filters
Journal Article
Hybrid Frequency Compensation to Improve Unity-Gain Bandwidth of Low-Voltage Low-Power CMOS Operational Amplifiers
TL;DR: A new hybrid frequency compensation (HFC) technique consisting of indirect compensation and compensation using unbalanced differential pairs for low-voltage low-power CMOS operational amplifiers (op amp) is proposed, which significantly improves frequency response and avoids instability when a large capacitive load at the output of the op amp must be handled.
Proceedings ArticleDOI
A power management system architecture for LF passive RFID tags
Fernando Paixão Cortes,Juan P. Brito,Everton Ghignatti,Alfredo Olmos,Fernando Chavez,Marcelo Lubaszewski +5 more
TL;DR: The architecture of a Power Management system for low-frequency passive RFID tags in a standard CMOS 0.18um technology is described, which makes use of the Self Cascode MOSFET (SCM) structure.
Proceedings ArticleDOI
Improving capacitive drive capability of miller compensated amplifier
M. Loikkanen,Juha Kostamovaara +1 more
TL;DR: In this paper, the authors compared a well-known technique of separating a capacitive load from the feedback path with a resistor to an alternative separation resistor technique and discussed limitations of both techniques.
Fast-Transient Low-Dropout Regulators in the IBM 0.13um BiCMOS Process
TL;DR: This thesis presents work on the design of 1.5V, 100mA low-dropout (LDO) regulators with fast transient responses in the IBM8HP 0.13μm BiCMOS process, and a new output capacitor-free architecture is introduced that can be fully integrated onto a chip.
Proceedings ArticleDOI
Shunt-feedback transimpedance amplifier in 0.18μm CMOS technology
TL;DR: In this article, a three-stage nested miller compensated (NMC) based design of low noise low power transimpedance amplifier for stable wideband operation is proposed, which can operate at frequency 20 KHz and produces an output of 1.4265V for ± 1.2 V input voltages dissipating only 2.9206 mW power at 27°C temperature.
References
More filters
Journal ArticleDOI
MOS operational amplifier design-a tutorial overview
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this paper, an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level is presented, focusing on CMOS amplifiers because of their more widespread use.
Journal ArticleDOI
A high performance low power CMOS channel filter
TL;DR: In this article, a new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die, and the chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW.
Journal ArticleDOI
High-performance NMOS operational amplifier
TL;DR: A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process.
Journal ArticleDOI
A single-chip CMOS PCM codec with filters
TL;DR: In this paper, a complete PCM codec using charge redistribution and switched-capacitor techniques is described, implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area.
Journal ArticleDOI
Low-Power High-Drive CMOS Operational Amplifiers
TL;DR: Low-power CMOS op amps with high-drive capability and good settling characteristics are described, suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.