Journal ArticleDOI
An improved frequency compensation technique for CMOS operational amplifiers
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TLDR
In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.Abstract:
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.read more
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Full On-Chip CMOS Low-Dropout Voltage Regulator
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References
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Journal ArticleDOI
A Single Chip Speech Synthesizer Using a Switched-Capacitor Multiplier
R. Gregorian,G. Amir +1 more
TL;DR: A single chip speech synthesizer was designed using a switched-capacitor multiplier to implement the LPC algorithm and is 218 mils on the side.
Journal ArticleDOI
A single chip speech synthesizer using a switched-capacitor multiplier
R. Gregorian,G. Amir +1 more
TL;DR: A single chip speech synthesizer was designed using a switched-capacitor multiplier to implement the LPC algorithm and is 218 mils on the side.