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Journal ArticleDOI

An improved frequency compensation technique for CMOS operational amplifiers

B.K. Ahuja
- 01 Dec 1983 - 
- Vol. 18, Iss: 6, pp 629-633
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TLDR
In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.
Abstract
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.

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Citations
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Proceedings ArticleDOI

Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth

TL;DR: A frequency compensation technique for achieving high 3dB bandwidth in two-stage operational amplifiers is demonstrated in this article, where the coupling capacitor and a PMOS transistor operating in triode region are connected between the output of the extra stage and the input of the second stage.
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TL;DR: In this paper, the authors presented a monitoring system with a handmade cross-type capacitive plantar pressure (CCPP) sensor, which includes a prototype detection module and a display interface, and implemented as a wearable device.
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A fast-settling 3 V CMOS buffer amplifier

TL;DR: In this article, a two-stage fast, power-efficient 3 V CMOS buffer amplifier with rail-to-rail input/output voltage ranges is presented, which is free of slew-rate limitation and its settling-time is quasi-independent on input step amplitude.
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Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

TL;DR: In this article, a CMOS power amplifier with rail-to-rail input and output, also suitable for low voltage applications, has been described, which uses Simple Miller Compensation with high bandwidth stage to robustly and power efficiently compensate the amplifier.
Proceedings ArticleDOI

Low dropout (LDO) voltage regulator design using split-length compensation

TL;DR: It is found that cascode and split-length compensation offer very similar performance, with the exception of quiescent current and area, and that stable designs are possible using single Miller compensation, whereas both cascodes require a Miller compensation network in parallel.
References
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Journal ArticleDOI

MOS operational amplifier design-a tutorial overview

TL;DR: In this paper, an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level is presented, focusing on CMOS amplifiers because of their more widespread use.
Journal ArticleDOI

A high performance low power CMOS channel filter

TL;DR: In this article, a new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die, and the chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW.
Journal ArticleDOI

High-performance NMOS operational amplifier

TL;DR: A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process.
Journal ArticleDOI

A single-chip CMOS PCM codec with filters

TL;DR: In this paper, a complete PCM codec using charge redistribution and switched-capacitor techniques is described, implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area.
Journal ArticleDOI

Low-Power High-Drive CMOS Operational Amplifiers

TL;DR: Low-power CMOS op amps with high-drive capability and good settling characteristics are described, suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.