Journal ArticleDOI
An improved frequency compensation technique for CMOS operational amplifiers
Reads0
Chats0
TLDR
In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.Abstract:
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.read more
Citations
More filters
Journal ArticleDOI
A 402-output TFT-LCD driver IC with power control based on the number of colors selected
TL;DR: In this article, a 402-output TFT-LCD driver integrated circuit with power control based on the number of colors to be displayed is described, where the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF.
Journal ArticleDOI
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS
TL;DR: By applying the proposed pseudo-cascode-compensation and bulk-biasing techniques in a two-stage opamp, the opamp's dc gain is increased by a factor of 4 (12 dB), its unit-gain frequency is increased, and its phase margin is maintained over a factors of 100 scaling in its bias current.
Journal ArticleDOI
A high-performance CMOS power amplifier
TL;DR: In this article, a high-performance CMOS power amplifier consisting of a new input stager especially suited to power amplifier applications and a variation on a class AB output stage is presented.
Journal ArticleDOI
An unconditionally stable two-stage CMOS amplifier
R.J. Reay,Gregory T. A. Kovacs +1 more
TL;DR: In this paper, the authors describe a two-stage CMOS amplifier that is stable for any capacitive load, achieved through the use of an optimized cascoded compensation topology, which allows independent optimization of drive capability, noise and systematic offset voltage.
Journal ArticleDOI
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
TL;DR: An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration and the proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture.
References
More filters
Journal ArticleDOI
MOS operational amplifier design-a tutorial overview
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this paper, an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level is presented, focusing on CMOS amplifiers because of their more widespread use.
Journal ArticleDOI
A high performance low power CMOS channel filter
TL;DR: In this article, a new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die, and the chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW.
Journal ArticleDOI
High-performance NMOS operational amplifier
TL;DR: A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process.
Journal ArticleDOI
A single-chip CMOS PCM codec with filters
TL;DR: In this paper, a complete PCM codec using charge redistribution and switched-capacitor techniques is described, implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area.
Journal ArticleDOI
Low-Power High-Drive CMOS Operational Amplifiers
TL;DR: Low-power CMOS op amps with high-drive capability and good settling characteristics are described, suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.