Journal ArticleDOI
An improved frequency compensation technique for CMOS operational amplifiers
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TLDR
In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.Abstract:
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.read more
Citations
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Journal ArticleDOI
A power management system architecture for LF passive RFID tags
Fernando Paixão Cortes,Juan P. Brito,Everton Ghignatti,Alfredo Olmos,Fernando Chavez,Marcelo Lubaszewski +5 more
TL;DR: A low power, low voltage power management (PM) system for low-frequency passive RFID tags in a standard CMOS 0.18 µm technology that monitors the available RF power at the LDO regulated output and flags when the power is low for different tag operation modes.
Indirect Compensation Techniques for Thr ee-Stage CMOS Op-Amps
Vishal Saxena,R. Jacob Baker +1 more
TL;DR: New design techniques for the realization of three-stage op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load.
Proceedings ArticleDOI
A 9Onm CMOS 0.28mm 2 1V 12b 40MS/s ADC with 0.39pJ/Conversion-Step
Kang-Jin Lee,Eun Seok Shin,Hee-Suk Yang,Ju-Hwa Kim,Pil-Un Ko,Il-Ryong Kim,Seung-Hoon Lee,Kyoung-Ho Moon,Jae-Whui Kim +8 more
TL;DR: In this paper, a 1V 12b 40MS/s pipelined ADC using a proposed two stage folded cascaded opamp for low voltage and a proposed frequency compensation technique for fast settling achieves a FOM of 0.39pJ/conversion step.
Proceedings ArticleDOI
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter
TL;DR: In this paper, a 10-b 30-MS/s low power CMOS pipelined analog-to-digital converter (ADC) is proposed, which avoids the use of on-chip clock voltage doubler, multithreshold voltage process, bootstrapped switch, or switched-opamp technique.
Proceedings ArticleDOI
Miller Compensation: Optimization with Current Buffer/Amplifier
TL;DR: A novel design-oriented approach for Miller compensation exploiting current buffer/amplifiers is described, which enables a simple design procedure to be outlined and applied to a two-stage CMOS OTA driving a large capacitive load.
References
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Journal ArticleDOI
MOS operational amplifier design-a tutorial overview
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this paper, an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level is presented, focusing on CMOS amplifiers because of their more widespread use.
Journal ArticleDOI
A high performance low power CMOS channel filter
TL;DR: In this article, a new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die, and the chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW.
Journal ArticleDOI
High-performance NMOS operational amplifier
TL;DR: A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process.
Journal ArticleDOI
A single-chip CMOS PCM codec with filters
TL;DR: In this paper, a complete PCM codec using charge redistribution and switched-capacitor techniques is described, implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area.
Journal ArticleDOI
Low-Power High-Drive CMOS Operational Amplifiers
TL;DR: Low-power CMOS op amps with high-drive capability and good settling characteristics are described, suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.