Proceedings ArticleDOI
Process variation study of Ground Plane SOI MOSFET
Mehdi Saremi,Behzad Ebrahimi,Ali Afzali Kusha,Mohammad Saremi +3 more
- pp 66-69
TLDR
In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated, and the results show that the GPS structure is more resistant against the variations when compared to the other two structures.Abstract:
In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.read more
Citations
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Omega shape channel LDMOS: A novel structure for high voltage applications
TL;DR: In this article, a new device structure for high breakdown voltage and low specific on resistance of the LDMOS device is proposed, which is called Omega-shape Channel LDMos (OCH-LDMOS).
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Periodic trench region in LDMOS transistor: A new reliable structure with high breakdown voltage
TL;DR: In this article, a new device structure for high breakdown voltage and low maximum lattice temperature of the LDMOS device is proposed, which uses a Si 3 N 4 trench region with open windows made by silicon in it.
Journal ArticleDOI
RF stability performance of SOI junctionless FinFET and impact of process variation
V. Jegadheesan,K. Sivasankaran +1 more
TL;DR: The developed RF stability model provides relation between critical frequency (f k) and small signal parameters which can be optimized for improved stability and provides optimized design guideline for operating SOI JLFinFET under RF range.
Journal ArticleDOI
Increase in the scattering of electric field lines in a new high voltage SOI MESFET
TL;DR: In this article, a new efficient technique to enhance the critical features of a silicon-on-insulator metal-semiconductor field effect transistor (SOI MESFET) applied in high voltage applications is presented.
Journal ArticleDOI
A new architecture of the dual gate transistor for the analog and digital applications
TL;DR: In this paper, a new nano-scale Metal Oxide Semiconductor Field Effect Transistor (SOI-MOSFET) was proposed for analog and digital applications.
References
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Journal ArticleDOI
Short-channel single-gate SOI MOSFET model
Kunihiro Suzuki,S. Pidin +1 more
TL;DR: In this article, the authors derived an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers.
Journal ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs
Toshinori Numata,Shinichi Takagi +1 more
TL;DR: In this paper, a comparative study on the device design method of the sub-threshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime is presented.
Journal ArticleDOI
The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs
M. Jagadesh Kumar,M. Siva +1 more
TL;DR: In this paper, the ground plane concept is used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length.
Proceedings ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs
TL;DR: In this article, the authors quantitatively studied device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and sub-threshold slope (SS) for fully depleted (FD) SOI MOSFETs under the sub-100 nm regime.
Journal ArticleDOI
Self-aligned implanted ground-plane fully depleted SOI MOSFET
Weize Xiong,Jean-Pierre Colinge +1 more
TL;DR: In this article, a method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described.