Journal ArticleDOI
The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs
M. Jagadesh Kumar,M. Siva +1 more
TLDR
In this paper, the ground plane concept is used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length.Abstract:
The ground plane (GP) concept is one of the techniques used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length. Therefore, if the GP is placed in the substrate (GPS), the buried oxide (BOX) thickness should be kept as small as possible which, however, results in an increased subthreshold slope. As a result, for sub-100-nm channel lengths, it is not possible to achieve both reduced DIBL and steep subthreshold slope using GPS. In this brief, a new device structure with the GP BOX is proposed to overcome the aforementioned shortcomings so that a reduced DIBL as well as an improved subthreshold slope can be obtained. Two-dimensional simulation is used to understand the efficacy of the proposed method.read more
Citations
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Journal ArticleDOI
Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits
TL;DR: In this article, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated, and the ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL).
Journal ArticleDOI
A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study
TL;DR: In this paper, a partial groundplane (PGPGP)-based MOSFET on a selective buried oxide (SELBOX) was proposed, and an extensive simulation study and a comparative analysis of the key characteristics of the PGP-SELBO, the SELBOX, and the conventional silicon-on-insulator (SOI) devices has been performed using the 2D device simulator Medici.
Journal ArticleDOI
Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)
Vadthiya Narendar,R. A. Mishra +1 more
TL;DR: In this article, a 3D analytical modeling of SOI multigate (GAA), triple-gate (TG), double-gate and double-Gate (DG) FinFETs is presented.
Journal ArticleDOI
High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor
TL;DR: In this paper, the authors present a III-V heterojunctionless TFET (H-JLTFET) for circuit applications, which is interfaced with group IV semiconductors.
Journal ArticleDOI
Offset voltage estimation model for latch-type sense amplifiers
TL;DR: The proposed model, which considers secondary effects, can accurately estimate σOS even when technology scales down, and is presented as the trend of the influence of secondary effects on the offset voltage with technology scaling.
References
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Journal ArticleDOI
Back-gated CMOS on SOIAS for dynamic threshold voltage control
TL;DR: A novel Silicon-On-Insulator-with-Active-Substrate (SOIAS)based technology was developed whereby a back-gate is used to control the threshold voltage of the front-gate and this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators.
Journal ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs
Toshinori Numata,Shinichi Takagi +1 more
TL;DR: In this paper, a comparative study on the device design method of the sub-threshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime is presented.
Proceedings ArticleDOI
Back gated CMOS on SOIAS for dynamic threshold voltage control
TL;DR: A novel SOI technology was developed whereby a back-gate was used to control the threshold voltage of the front-gate, and this concept was demonstrated on a selectively scaled CMOS process.
Proceedings ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs
TL;DR: In this article, the authors quantitatively studied device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and sub-threshold slope (SS) for fully depleted (FD) SOI MOSFETs under the sub-100 nm regime.
Journal ArticleDOI
Self-aligned implanted ground-plane fully depleted SOI MOSFET
Weize Xiong,Jean-Pierre Colinge +1 more
TL;DR: In this article, a method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described.
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Self-aligned implanted ground-plane fully depleted SOI MOSFET
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