Proceedings ArticleDOI
Process variation study of Ground Plane SOI MOSFET
Mehdi Saremi,Behzad Ebrahimi,Ali Afzali Kusha,Mohammad Saremi +3 more
- pp 66-69
TLDR
In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated, and the results show that the GPS structure is more resistant against the variations when compared to the other two structures.Abstract:
In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.read more
Citations
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Journal ArticleDOI
Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling
TL;DR: In this article, the drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate-gate charge coupling is investigated at pillar thicknesses in the range of 200-10 nm.
Journal ArticleDOI
Design and Performance Analysis of HybridSELBOX Junctionless FinFET
TL;DR: In this paper, the performance of a selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure was analyzed and compared with the conventional and hybrid (or inverted-T ) JLFinFETs.
Journal ArticleDOI
Comparative Investigation on Bias Dependent RF Performance of SOI Substrates
References
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Journal ArticleDOI
Short-channel single-gate SOI MOSFET model
Kunihiro Suzuki,S. Pidin +1 more
TL;DR: In this article, the authors derived an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers.
Journal ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs
Toshinori Numata,Shinichi Takagi +1 more
TL;DR: In this paper, a comparative study on the device design method of the sub-threshold slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime is presented.
Journal ArticleDOI
The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs
M. Jagadesh Kumar,M. Siva +1 more
TL;DR: In this paper, the ground plane concept is used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length.
Proceedings ArticleDOI
Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs
TL;DR: In this article, the authors quantitatively studied device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and sub-threshold slope (SS) for fully depleted (FD) SOI MOSFETs under the sub-100 nm regime.
Journal ArticleDOI
Self-aligned implanted ground-plane fully depleted SOI MOSFET
Weize Xiong,Jean-Pierre Colinge +1 more
TL;DR: In this article, a method for fabricating a back-gate ground plane underneath a thin-film silicon-on-insulator (SOI) MOSFET is described.