Journal ArticleDOI
TSV Redundancy: Architecture and Design Issues in 3-D IC
Ang-Chih Hsieh,TingTing Hwang +1 more
TLDR
A redundant TSV architecture with reasonable cost is proposed in this paper and analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.Abstract:
3-D technology provides many benefits including high density, high bandwidth, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3-D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost is proposed in this paper. Based on probabilistic models, some interesting findings are reported. First, the number of failed TSVs in a tier is usually less than 2 when the number of TSVs in a tier is less than 1000 and less than 5 when the number of TSVs in a tier is less than 10000. Assuming that there are at most 2-5 failed TSVs in a tier. With one redundant TSV allocated to one TSV block, our proposed structure leads to 90% and 95% recovery rates for TSV blocks of size 50 and 25, respectively. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV to 99.4%.read more
Citations
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Journal ArticleDOI
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization
TL;DR: This paper presents a discrete particle swarm optimization (PSO)-based strategy to map applications on both 2-D and 3-D mesh-connected Networks-on-Chip, and its results are superior to those from reported techniques.
Journal ArticleDOI
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs
Li Jiang,Qiang Xu,Bill Eklow +2 more
TL;DR: A novel TSV repair framework is presented, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction, which can improve the manufacturing yield for 3-D-stacked ICs.
Journal ArticleDOI
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip
TL;DR: A machine-learning-inspired predictive design methodology for energy-efficient and reliable many-core architectures enabled by 3-D integration and a computationally efficient spare-vertical link (sVL) allocation algorithm based on a state-space search formulation are proposed.
Journal ArticleDOI
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
TL;DR: A honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield is proposed and the simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rates for highly clustered faults.
References
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Journal ArticleDOI
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Journal ArticleDOI
Demystifying 3D ICs: the pros and cons of going vertical
W.R. Davis,John W. Wilson,S. Mick,Jian Xu,Hao Hua,C. Mineo,A.M. Sule,Michael B. Steer,Paul D. Franzon +8 more
TL;DR: In this paper, the authors present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule.
Journal ArticleDOI
Three-dimensional integrated circuits
Anna W. Topol,D.C. La Tulipe,L. Shi,David J. Frank,K. Bernstein,Steven E. Steen,Arvind Kumar,G. U. Singco,A. M. Young,K. W. Guarini,Meikei Ieong +10 more
TL;DR: The process steps and design aspects that were developed at IBM to enable the formation of stacked device layers are reviewed, including the descriptions of a glass substrate process to enable through-wafer alignment and a single-damascene patterning and metallization method for the creation of high-aspect-ratio capability.
Journal ArticleDOI
Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs
TL;DR: Three-dimensional integrated circuits offer significant improvements over two-dimensional circuits, and promise a solution to the severe problems that are being, and will be, encountered as monolithic process geometries are reduced to below 65 nm.
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