Showing papers on "Bandgap voltage reference published in 2020"

A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology

Abstract: Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. V BE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes $51.8\mu \mathrm{W}$ power from 1V power supply and occupies $2478\ \mu \mathrm{m}^{2}$ silicon area.

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

Abstract: An ultra-low quiescent current dual-mode buck converter system is designed for IoT application, which includes a double clock time (DCT) and a pulse-width-modulation (PWM) control modes. The proposed DCT mode can reduce the conversion loss over a wide loading range from nA-to-mA and achieve seamless mode transition from DCT to PWM control. Implemented in a $0.18\mu \text{m}$ CMOS, this converter achieves a peak efficiency of 92.7%/94.7% in DCT/PWM and >80% efficiency from $10~\mu $ A to 50 mA (5000x), with a wide input voltage from 2 V to 5 V. A quiescent current of 470 nA including bandgap voltage reference and internal oscillator is achieved. The DCT-to-PWM mode selection mechanism achieves an undershoot of 80 mV at $11~\mu \text{s}$ recovery time when load current jumps from $6.67~\mu \text{A}$ to 50 mA.

A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within −40 °C to 120 °C

Abstract: This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$ . Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming.

An 18-nA Ultra-Low-Current Resistor-Less Bandgap Reference for 2.8 V–4.5 V High Voltage Supply Li-Ion-Battery-Based LSIs

Abstract: This brief presents a resistor-less bandgap reference (BGR) with ultra-low current consumption, which can be applied in energy harvesting systems that use lithium-ion (Li-ion) batteries as intermediate energy storage. The system supply voltage is defined by the output voltage of the Li-ion battery, which is usually from 3 V to 4.2 V. The BGR circuit working in this kind of system needs to withstand a high supply voltage while consuming nano-watt power. In this brief, differential pairs are first used in a low-power BGR circuit as a voltage duplicator to achieve duplication of both the proportional-to-absolute-temperature (PTAT) voltage and the trimming network, which can reduce the complexity of the structure and the chip area of the trimming network. The total current consumption of the BGR is around 18 nA for different supply voltages ranging from 2.8 V to 4.5 V. Fabricated in a 0.35- ${\mu }\text{m}$ CMOS process, the BGR circuit generates a 1.17 V bandgap voltage with an average temperature coefficient of 65 ppm/°C and a line regulation of 0.112 %/V.

A High-Precision Bandgap Reference With a V-Curve Correction Circuit

Abstract: In this study, a precision bandgap reference with a v-curve correction (VCC) circuit is presented. The proposed VCC circuit generates a correction voltage to reduce the temperature drift of the reference voltage and achieves a low temperature coefficient (TC) in a wide temperature range. The proposed bandgap reference was designed and fabricated using a standard TSMC 0.18- $\mu \text{m}$ 1P6M CMOS technology with an active area of 0.0139 mm2. The measured results show that the proposed bandgap reference achieves a TC of 1.9–5.28 ppm/°C over a temperature range of −40°C to 140 °C at a supply voltage of 1.8 V. In addition, the circuit demonstrated a line regulation of 0.033 %/V for supply voltages of 1.2 – 1.8 V at room temperature.

A 2–10 MHz GaN HEMTs Half-Bridge Driver With Bandgap Reference Comparator Clamping and Dual Level Shifters for Automotive Applications

Abstract: Gallium nitride (GaN) high electron mobility transistors (HEMTs) are promising power devices due to their excellent characteristics. However, GaN HEMTs have vulnerable gates that are susceptible to noise and voltage spikes, limiting their implementation in power converters. This paper presents a GaN HEMTs half-bridge driver with bandgap reference comparator clamping (BGRCC) and dual level shifters (DLS) for high switching frequency automotive applications. The BGRCC scheme can adaptively clamp the bootstrap rail voltage at an appropriate level with acceptable voltage ripples, which guarantees the safety of high-side GaN HEMT. Meanwhile, DLS scheme is applied in both the high- and low-side driving path to effectively drive the GaN HEMTs with low propagation delay and high dv / dt immunity. The proposed driver is fabricated in 0.18 μm high voltage bipolar-complementary metaloxide semiconductor (CMOS)-double-diffused metaloxide semiconductor (DMOS) process and can support 2–10 MHz operating. The functionality and performance are verified by experimental results. A buck converter utilizing this driver with GaN HEMTs can achieve maximum efficiency of 91.58% with quite electromagnetic interference behavior in the 16.5-W output power rating when operating at 2 MHz, which is superior to conventional silicon-based power converters and suitable for automotive applications.

Wide-Supply-Voltage-Range CMOS Bandgap Reference for In Vivo Wireless Power Telemetry

Abstract: The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35-μm SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV/V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of −54 dB, and temperature coefficient of 11.9 ppm/°C in the temperature range of 25 to 100 °C.

A BGR-Recursive Low-Dropout Regulator Achieving High PSR in the Low- to Mid-Frequency Range

Abstract: This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5- μ m 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C OUT ≥ 1 μ F. The proposed LDO consumes only 50 μ A at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

Abstract: A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters

Abstract: Digital coherent optical transmission technologies are attracting much attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for which transceivers that can handle symbol rates over 64GBaud and modulation orders over 16-QAM are necessary. Regarding the transmitter, the Optical Internetworking Forum (OIF) is discussing a 64GBaud-class high-bandwidth coherent driver modulator (HB-CDM), which is a broadband electro-optic (EO) front-end module containing optical modulator drivers and Mach-Zehnder modulators (MZMs) [1]. In addition to operating speed, power consumption is also important because it limits the form factor. It is important to reduce the power consumption of the optical modulator driver - one of the most power-hungry blocks in the transmitter - while maintaining a sufficient bandwidth (BW) and an optimal linear voltage swing to drive the MZMs. The temperature dependence of the RF characteristics is also important for practical use because the transceivers will be operated long term in various environments. Here, we present a 65nm-CMOS linear driver IC in which shunt and series multi-peaking techniques with small-footprint inductors extend the BW, and a stacked current-reuse architecture reduces power consumption with voltage from a single power supply. We compensated for temperature dependence by combining an adjustable bandgap reference (BGR) and resistors with a temperature gradient. The driver is equipped with an on-chip DC block with a bias network at inputs and includes a gain control (GC), emphasis control (EMP), a peak detector (PD), and temperature monitor (TM), all controlled by a serial peripheral interface (SPI). A four-channel driver for dual-polarization (DP) IQ modulation is monolithically integrated on one chip, and is co-packaged with a four-channel InP-based MZM as an HB-CDM. The module successfully demonstrated 64Gbaud DP-32QAM (gross bit rate of 640Gb/s).

Ultra Miniature 1850 μm 2 Ring Oscillator Based Temperature Sensor

Abstract: Temperature sensing is a necessity in semiconductor products, in order to monitor die behavior and avoid thermal runaway, while achieving high performance. Integrated sensors are used to monitor and regulate numerous hot spots across the die to prevent reliability issues. As the hot spots are in the most congested areas of the chip, it is also desirable for the sensors to have a very small sensing element which can be placed close to the hot-spot. The sensors are also used to monitor the coldest parts of the chip to determine the required Vdd level. These functions require the sensors to be very compact as well as low energy. A ring oscillator based temperature sensor is presented in TSMCs 65nm node, with an area of 1850μm 2 . This sensor has a novel structure which is similar to a bandgap reference, with the BJT devices replaced by scaled ring oscillators. The sensor exhibits a 3-sigma inaccuracy of ±1°C near the throttle point, for hot-spot sensing, and ± 2.5°C over the -10°C to 110°C range. The power supply rejection is 2.4°C/V. The sensor consumes 0.94nJ per 10μs conversion and achieves a resolution FOM of 96pJ-K 2 .

A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18- μ m CMOS

Abstract: In this letter, we propose a bandgap reference (BGR) with a single BJT branch and a PTAT-embedded amplifier with a cascode Miller frequency compensation. As implemented in 0.18- $\mu \text{m}$ CMOS, the proposed BGR occupies a small area of 0.0082 mm2 and low power consumption of 192 nW while achieving voltage spread ( $\sigma /\mu $ ) of 0.33% and temperature coefficient of 26.3 ppm/°C over −40°C~140°C, without any trimming.

A 180 nm Self-biased Bandgap Reference with High PSRR Enhancement

Abstract: In this paper, an improved self-biased bandgap reference (BGR) with high power supply rejection ratio (PSRR) is presented. An operational amplifier constructing feedback loop is multiplexed with the generation of positive temperature coefficient (TC) voltage for lower power consumption, where an offset voltage is adopted to achieve proportional to absolute temperature (PTAT) voltage. With the temperature-independent reference generation, two feedback loops are realized at the same time for PSRR enhancement, which form a local negative feedback loop (LNFL) and a global self-biased loop (GSBL). The proposed BGR is implemented in a 180 nm BCD technology, whose results show that the generated reference voltage is 2.506 V, and the TC is 25 ppm/°C in the temperature range of −55 to 125 °C. The line sensitivity (LS) is 0.08 ‰/V. Without any filter capacitor, the PSRR is 76 dB at low frequencies, over 46 dB up to 1 MHz.

A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, −0.12% for Battery Monitoring Applications

Abstract: This paper presents a single-trim switched-capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. A β-compensation technique, which is used in conjunction with mismatch averaging, and a discrete time (DT) domain curvature correction are proposed to minimize non-PTAT errors. The remaining PTAT errors are cancelled out by using a single room-temperature (27°C) trimming. Implemented in a 0.18μm CMOS, the proposed SC BGR achieves a 3σ inaccuracy of +0.02%, −0.12% and an average temperature coefficient (TC) of 4.3ppm/°C from −40°C to 125°C. It consumes 17μΑ at 27°C from 1.8V supply.

Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity

Abstract: Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

An 8-nW Resistor-Less Bandgap Reference Based on a Single-Branch Floating PTAT Voltage

Abstract: This letter presents an ultra low-power resistor-less bandgap reference circuit, which is based on the topology of a single-branch floating proportional-to-absolute-temperature (PTAT) voltage. By using a cascode high impedance current bias technique, the single-branch PTAT voltage can be directly floating on the complementary-to-absolute-temperature (CTAT) voltage generated by the $V_{EB}$ of the bipolar transistor. Ultra low power consumption is realized by the simple topology in the proposed method, which only needs a few current branches. Fabricated in 0.13- $\mu \text{m}$ CMOS process, this letter generates a 1.252-V bandgap reference voltage. The total power consumption is 8.26 nW with a 1.4-V supply voltage. Without a resistor, this letter can achieve a small active area of 0.017 mm2. The average value of the temperature coefficient is 68 ppm/°C from −20 °C to 110 °C, and the line regulation is 0.019 %/V.

Total Dose Effects on Negative and Positive Low-Dropout Linear Regulators

Abstract: Total ionizing dose (TID) functional failure analysis on positive and negative low-dropout linear voltage regulators is performed. Two parts have been chosen for this article: the LP2953 positive regulator and the LT1175 negative regulator. Different failure mechanisms are observed, which can be modeled with radiation-enabled SPICE simulations. The simulation results are shown to compare well with experimental data. Both voltage regulators contain three blocks, essential for accurate modeling: a bandgap reference, a power pass transistor, and an error amplifier. In this article, simulations were performed on each block independently to analyze the trends in parametric degradation after radiation exposure and describe the failure mechanisms. This article identifies the bandgap circuitry as the primary cause of failure for the negative regulator while degradations in all blocks contribute to the TID response of circuits.

Linearity Boosting Technique Analysis for a Modified Current-Mode Bandgap Reference

Abstract: This paper presents a detailed analysis of an effective method to improve the linearity and, consequently, the temperature insensitivity of the output characteristic of current processing based bandgap references. The described technique is shown to be successful on a circuit which generates a temperature-invariant current of approximately 1 µA which has been designed and extensively simulated in a standard 130-nm CMOS process in the -40°C to 125°C temperature range. The circuit nominal supply voltage is 1.5 V and it has a total power consumption of about 5 µW. The analyzed linearity boosting technique, applied to the proposed circuit, provides a temperature sensitivity of the output current as low as 1.7 ppm/°C in the considered range, making it suitable for a lot of different precision applications that require a highly stable current signal with respect to temperature.

An Automotive Low-Power EMC Robust Brokaw Bandgap Voltage Reference

Abstract: This article proposes an electromagnetic compatibility improved bandgap voltage reference with a low current consumption of only 3.5 μA in an automotive environment with a wide temperature range from –40 °C to 160 °C and a high electromagnetic interference (EMI) robustness. The proposed reference is based on the well-known Brokaw bandgap with only five bipolar transistors in the bandgap core including collector current leakage compensation. We analyzed parasitic effects in the bandgap core such as the influence of parasitic capacitances between the substrate and the collectors of these bipolar transistors as well as the impact of the operational amplifier. We made recommendations on how to improve the bandgap EMI robustness. Simulation results were compared with measurements on a test chip. The measurement results showed excellent EMI robustness.

Recent Developments in Bandgap References for Nanometer CMOS Technologies

Abstract: This paper provides a short overview about evolving sub-bandgap references, and the related challenges in modern FinFET nodes. Specifically, we present a simple yet innovative concept to generate PTAT and CTAT voltages through “capacitive bias”: In replacement of the classical BJT, the active bulk diode is utilized and forward biased by a charge-pump. Two capacitors are discharged across the diode for different time periods, which precisely defines the respective current densities. The sampled diode voltages are then combined by charge sharing or addition, to provide a robust reference. A reverse bandgap reference using this architecture features an untrimmed accuracy of ± 0.73% (3$\sigma$), consuming only 21nA in a 16nm FinFET process. The simple structures feature intrinsic supply rejection down to 0.85V and a digital-alike operation.

A Constant g m Current Reference Generator with Purely Off-Chip Resistor

Abstract: Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We proposed an on-chip reference generator with a fully off-chip resistor which has less sensitivity to the process variations. MonteCarlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in 0.18 μm CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor.

A 0.7 V 5 nW CMOS sub-bandgap voltage reference without resistors

Abstract: A 0.7 V 5 nW CMOS Sub-Bandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementary-to-absolute-temperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and sub-threshold transistors. The sub-Bandgap voltage reference is implemented in a 0.18-µm CMOS process. Measured results show that the reference can run with 0.7 V supply voltage, while the power consumption is only 5 nW at room temperature, the area is 0.026 mm2 and the PSRR of better than − 48 dB over the full frequency range is achieved. The average temperature coefficient is 49 ppm/°C with a temperature range of − 40 to 125 °C. Also the line sensitivity is 0.02%/V.

Application of Artificial Neural Networks to the Automation of Bandgap Reference Synthesis

Abstract: Bandgap voltage references are present in virtually every analog/mixed-signal system. However, their design still remains a time-consuming procedure that requires extensive designer expertise and validation. In this paper, an automated bandgap synthesis procedure is used to generate a dataset that maps the specifications of the synthesized bandgap reference circuit to their corresponding designer's degrees of freedom. This dataset is then used to train a neural network to predict the choice of the degrees of freedom in order to meet arbitrary circuit specifications specified by the user including variations due to design corners and random mismatch. The automated bandgap synthesis procedure uses precomputed look-up tables rather than invoking a circuit simulator in the loop, which enables generating a large dataset of training examples in short time. The choice of the degrees of freedom predicted by the neural network is then re-fed to the bandgap synthesis procedure to verify the accuracy of the prediction and obtain the complete solution of the synthesized circuit. The results demonstrate that the trained neural network is capable of making successful predictions of good accuracy in a wide multi-dimensional design space.

A Simple Bandgap Reference Based on V GO Extraction with Single-Temperature Trimming

Abstract: This paper presents a simple structure to extract V GO , the silicon bandgap voltage at zero Kelvin Based on a traditional Kuijk structure, a third diode with a temperature constant current is used to extract the curvature TlnT term A novel Gm cell-based voltage summer is proposed to perform the curvature correction A single temperature trimming method is implemented to trim out PTAT errors and calibrate the gain of the summer The bandgap reference circuit is simulated in the UMC 65nm process With the proposed trimming method, a temperature coefficient less than 10 ppm/°C from −40 °C to 125 °C can be achieved

An Accurate 0.55-V 2.6- μ W Voltage-Level Detector

Abstract: A CMOS voltage-level detector (VLD) circuit is proposed for Internet-of-Things systems which operates near the minimum energy point. It can accurately detect $V_{\text {CC}}$ levels of 550–640 mV, making it one of the lowest voltage VLDs reported to date. A novel pull-up circuit is utilized to accurately detect fast $V_{\text {CC}}$ ramps of 10’s of microseconds, which are faster than the power-up of the VLD itself. This feature enables it to operate at a low power consumption of 2.6 uW. A low voltage, charge-pumped bandgap reference is utilized with a highly accurate comparator to achieve a 35-mV variation across temperature and a random variation sigma of 1.68 mV. This circuit is one of the lowest voltage, most highly accurate, and fastest ramp-detect VLDs that have been reported in the literature.