Showing papers on "Bipolar junction transistor published in 2000"

The Art of Analog Layout

Abstract: (NOTE: Each chapter concludes with "Summary" and "Exercises.") 1. Device Physics. Semiconductors. Generation and Recombination. Extrinsic Semiconductors. Diffusion and Drift. PN Junctions. Depletion Regions. PH Diodes. Schottky Diodes. Zener Diodes. Ohmic Contacts. Bipolar Junction Transistors. Beta. I-V Characteristics. MOS Transistors. Threshold Voltage. I-V Characteristics. JFET Transistors. 2. Semiconductor Fabrication. Silicon Manufacture. Crystal Growth. Wafer Manufacturing. The Crystal Structure of Silicon. Photolithography. Photoresists. Photomasks and Reticles. Patterning. Oxide Growth and Removal. Oxide Growth and Deposition. Oxide Removal. Other Effects of Oxide Growth and Removal. Local Oxidation of Silicon (LOCOS). Diffusion and Ion Implantation. Diffusion. Other Effects of Diffusion. Ion Implantation. Silicon Deposition. Epitaxy. Polysilicon Deposition. Metallization. Deposition and Removal of Aluminum. Refractory Barrier Metal. Silicidation. Interlevel Oxide, Interlevel Nitride, and Protective Overcoat. Assembly. Mount and Bond. Packaging. 3. Representative Processes. Standard Bipolar. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Polysilicon-Gate CMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. Analog BiCMOS. Essential Features. Fabrication Sequence. Available Devices. Process Extensions. 4. Failure Mechanisms. Electrical Overstress. Electrostatic Discharge (ESD). Electromigration. The Antenna Effect. Contamination. Dry Corrosion. Mobile Ion Contamination. Surface Effects. Hot Carrier Injection. Parasitic Channels and Charge Spreading. Parasitics. Substrate Debiasing. Minority-Carrier Injection. 5. Resistors. Resistivity and Sheet Resistance. Resistor Layout. Resistor Variability. Process Variation. Temperature Variation. Nonlinearity. Contact Resistance. Resistor Parasitics. Comparison of Available Resistors. Base Resistors. Emitter Resistors. Base Pinch Resistors. High-Sheet Resistors. Epi Pinch Resistors. Metal Resistors. Poly Resistors. NSD and PSD Resistors. N-Well Resistors. Thin-Film Resistors. Adjusting Resistor Values. Tweaking Resistors. Trimming Resistors. 6. Capacitors. Capacitance. Capacitor Variability. Process Variation. Voltage Modulation and Temperature Variation. Capacitor Parasitics. Comparison of Available Capacitors. Base-Emitter Junction Capacitors. MOS Capacitors. Poly-Poly Capacitors. Miscellaneous Styles of Capacitors. 7. Matching of Resistors and Capacitors. Measuring Mismatch. Causes of Mismatch. Random Statistical Fluctuations. Process Biases. Pattern Shift. Variations in Polysilicon Etch Rate. Diffusion Interactions. Stress Gradients and Package Shifts. Temperature Gradients and Thermoelectrics. Electrostatic Interactions. Rules for Device Matching. Rules for Resistor Matching. Rules for Capacitor Matching. 8. Bipolar Transistors. Topics in Bipolar Transistor Operation. Beta Rolloff. Avalanche Breakdown. Thermal Runaway and Secondary Breakdown. Saturation in NPN Transistors. Saturation in Lateral PNP Transistors. Parasitics of Bipolar Transistors. Standard Bipolar Small-Signal Transistors. The Standard Bipolar NPN Transistor. The Standard Bipolar Substrate PNP Transistor. The Standard Bipolar Lateral PNP Transistor. High-Voltage Bipolar Transistors. Alternative Small-Signal Bipolar Transistors. Extensions to Standard Bipolar. Bipolar Transistors in a CMOS Process. Advanced-Technology Bipolar Transistors. 9. Applications of Bipolar Transistors. Power Bipolar Transistors. Failure Mechanisms of NPN Power Transistors. Layout of Power NPN Transistors. Saturation Detection and Limiting. Matching Bipolar Transistors. Random Variations. Emitter Degeneration. NBL Shadow. Thermal Gradients. Stress Gradients. Rules for Bipolar Transistor Matching. Rules for Matching NPN Transistors. Rules for Matching Lateral PNP Transistors. 10. Diodes. Diodes in Standard Bipolar. Diode-Connected Transistors. Zener Diodes. Schottky Diodes. Diodes in CMOS and BiCMOS Processes. Matching Diodes. Matching PN Junction Diodes. Matching Zener Diodes. Matching Schottky Diodes. 11. MOS Transistors. Topics in MOS Transistor Operation. Modeling the MOS Transistor. Parasitics of MOS Transistors. Self-Aligned Poly-Gate CMOS Transistors. Coding the MOS Transistor. N-Well and P-Well Processes. Channel Stops. Threshold Adjust Implants. Scaling the Transistor. Variant Structures. Backgate Contacts. 12. Applications of MOS Transistors. Extended-Voltage Transistors. LDD and DDD Transistors. Extended-Drain Transistors. Multiple Gate Oxides. Power MOS Transistors. Conventional MOS Power Transistors. DMOS Transistors. The JFET Transistor. Modeling the JFET. JFET Layout. MOS Transistor Matching. Geometric Effects. Diffusion and Etch Effects. Thermal and Stress Effects. Common-Centroid Layout of MOS Transistors. Rules for MOS Transistor Matching. 13. Special Topics. Merged Devices. Flawed Device Mergers. Successful Device Mergers. Low-Risk Merged Devices. Medium-Risk Merged Devices. Devising New Merged Devices. Guard Rings. Standard Bipolar Electron Guard Rings. Standard Bipolar Hole Guard Rings. Guard Rings in CMOS and BiCMOS Designs. Single-Level Interconnection. Mock Layouts and Stick Diagrams. Techniques for Crossing Leads. Types of Tunnels. Constructing the Padring. Scribe Streets and Alignment Markers. Bondpads, Trimpads, and Testpads. ESD Structures. Selecting ESD Structures. 14. Assembling the Die. Die Planning. Cell Area Estimation. Die Area Estimation. Gross Profit Margin. Floorplanning. Top-Level Interconnection. Principles of Channel Routing. Special Routing Techniques. Electromigration. Minimizing Stress Effects. Appendix A: Table of Acronyms Used in the Text. Appendix B: The Miller Indices of a Cubic Crystal. Appendix C: Sample Layout Rules. Appendix D: Mathematical Derivations. Appendix E: Sources for Layout Editor Software. Index.

Fabrication and performance of GaN electronic devices

Abstract: GaN and related materials (especially AlGaN) have recently attracted a lot of interest for applications in high power electronics capable of operation at elevated temperatures. Although the growth and processing technology for SiC, the other viable wide bandgap semiconductor material, is more mature, the AlGaInN system offers numerous advantages. These include wider bandgaps, good transport properties, the availability of heterostructures (particularly AlGaN/GaN), the experience base gained by the commercialization of GaN-based laser and light-emitting diodes and the existence of a high growth rate epitaxial method (hydride vapor phase epitaxy) for producing very thick layers or even quasi-substrates. These attributes have led to rapid progress in the realization of a broad range of GaN electronic devices, including heterostructure field effect transistors (HFETs), Schottky and p–i–n rectifiers, heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs) and metal-oxide semiconductor field effect transistors (MOSFETs). This review focuses on the development of fabrication processes for these devices and the current state-of-the-art in device performance, for all of these structures. We also detail areas where more work is needed, such as reducing defect densities and purity of epitaxial layers, the need for substrates and improved oxides and insulators, improved p-type doping and contacts and an understanding of the basic growth mechanisms.

On the performance limits for Si MOSFETs: a theoretical study

Abstract: Performance limits of silicon MOSFETs are examined by a simple analytical theory augmented by self-consistent Schrodinger-Poisson simulations. The on-current, transconductance, and drain-to-source resistance in the ballistic limit (which corresponds to the channel length approaching zero) are examined. The ballistic transconductance in the limit that the oxide thickness approaches zero is also examined. The results show that as the channel length approaches zero (which corresponds to the ballistic limit), the on-current and transconductance approach finite limiting values and the channel resistance approaches a finite minimum value. The source velocity can be as high as about 1.5/spl times/10/sup 7/ cm/s. The limiting on-current and transconductance are considerably higher than those deduced experimentally by a previous study of MOSFETs with channel lengths greater than 0.2 /spl mu/m. At the same time, the transconductance to current ratio is substantially lower than that of a bipolar transistor.

Semiconductor physics and applications

Abstract: Preface 1. Basic characteristics of semiconductors 2. Electronic energy bands: Basic theory 3. Electronic energy bands: Semiconductors 4. Kinematics and dynamics of electrons and holes in energy bands 5. Electronic effects of impurities 6. Semiconductor statistics 7. Lattice vibrations in semiconductors 8. Charge carrier scattering and transport properties 9. Surface properties of semiconductors 10. Optical properties of semiconductors 11. Magneto-optical and electro-optical phenomena 12. P-N junctions in semiconductors 13. Bipolar junction transistor 14. Semiconductor lasers and photodevices 15. Heterostructures: Electronic states 16. Phonons in superlattices 17. Optical properties of heterostructures 18. Transport properties of heterostructures 19. Metal-semiconductor devices 20. Applications of semiconductor heterostructures

RF/Microwave Circuit Design for Wireless Applications

Abstract: From the Publisher: With wireless technology rapidly exploding, there is a growing need for circuit design information specific to wireless applications Presenting a single-source guidebook to this dynamic area, industry expert Ulrich Rohde and writer David Newkirk provide researchers and engineers with a complete set of modeling, design, and implementation tools for tackling even the newest IC technologies They emphasize practical design solutions for high-performance devices and circuitry, incorporating ample examples of novel and clever circuits from high-profile companies They also provide excellent appendices containing working models and CAD-based applications RF/Microwave Circuit Design for Wireless Applications offers: Introduction to wireless systems and modulation typesA systematic approach that differentiates between designing for battery-operated devices and base-station designA comprehensive introduction to semiconductor technologies, from bipolar transistors to CMOS to GaAs MESFETsClear guidelines for obtaining the best performance in discrete and integrated amplifier designDetailed analysis of available mixer circuits applicable to the wireless frequency rangeIn-depth explanations of oscillator circuits, including microwave oscillators and ceramic-resonator-based oscillatorsA thorough evaluation of all components of wireless synthesizers

Understanding semiconductor devices

Abstract: Part 1 Resistors: introduction to semiconductors the basics - resistor structure and drift current insight into conducitivity ingredients - chemical-bond model making a semiconductor resistor - lithography and diffusion carrier mobility energy-band model capacitors - reverse-biased P-N junction and MOS structure. Part 2 Basic applications: reverse-biased P-N junction $C$--$V$ dependence of the reverse-biased P-N junction - solving the Poisson equation SPICE parameters and their measurement metal-oxide-semiconductor (MOS) capacitor and thermal oxide. Part 3 Diodes: forward-biased P-N junction and metal-semiconductor contact rectifying diodes - fundamental effects and models SPICE models and parameters, stored charge capacitance, and temperature effects reference diodes - breakdown phenomena Schottky diodes - metal-semiconductor contact. Part 4 Basics of transistor applications: analog circuits digital circuits. Part 5 MOSFET: MOSFET principles MOSFET technologies MOSFET modelling SPICE parameters and parasitic elements. Part 6 BJT: BJT principles bipolar IC technologies BJT modelling SPICE parameters parasitic elements not included in device models. Part 7 advanced and specific IC devices and technologies: deep sub-micron MOSFET memory devices silicon-on-insulator (SOI) technology BICMOS technolgoy. Part 8 Photographic devices: light emitting diodes (LED) - carrier recombination photodetectors and solar cells - external carrier generation lasers. Part 9 Microwave FETs and diodes: gallium-arsenide versus silicon JFET MESFET HEMT negative resistance diodes. Part 10 Power devices: power devices in switch-mode power circuits power diodes power MOSFET IGBT thyristor. Part 11 Semiconductor device reliability basic reliability concepts failure mechanisms reliability screening reliability measurement. Part 12 Quantum mechanics: wave function Heisenberg uncertainty principle Schrodinger equation. Appendixes: basic integrated circuit concepts and economics crystal lattices, planes, and directions Hall effect and summary of kinetic phenomena summary of equations and key points list of Selected symbols answers to selected problems.

Molecular wire transistor (MWT)

Abstract: Bipolar and field effect molecular wire transistors are provided. The molecular wire transistor comprises a pair of crossed wires, with at least one of the wires comprising a doped semiconductor material. The pair of crossed wires forms a junction where one wire crosses another, one wire being provided with Lewis acid functional groups and the other wire being provided with Lewis base functional groups. If both wires are doped semiconductor, such as silicon, one is P-doped and the other is N-doped. One wire of a given doping comprises the emitter and collector portions and the other wire comprises the base portion, which is formed by modulation doping on the wire containing the emitter and collector at the junction where the wires cross and between the emitter and collector portions, thereby forming a bipolar transistor. Both NPN and PNP bipolar transistors may be formed. Analogously, one wire may comprise doped semiconductor, such as silicon, and the other wire a metal, the doped silicon wire forming the source and drain and the metal wire forming the gate by modulation doping on the doped silicon wire where the wires cross, between the source and drain, to form a field effect transistor. Both P-channel and N-channel FETs may be formed. The construction of both bipolar transistors and FETs on a nanometer scale, which are self-aligned and modulation-doped, is thereby enabled.

The temperature characteristics of bipolar transistors fabricated in CMOS technology

Abstract: This paper presents the results of an experimental investigation of the temperature characteristics of bipolar transistors fabricated in CMOS technology. These results have to be known and understood to enable the design of high-performance temperature sensors and bandgap references in CMOS integrated circuits. The non-idealities of proportional to the absolute temperature voltage (VPTAT) have been studied, and the results show that we can generate accurate PTAT voltages by optimizing the operating condition and layout of the transistors (error

Direct extraction technique to derive the junction temperature of HBT's under high self-heating bias conditions

Abstract: A new technique is presented that can directly extract the mean device junction temperature of heterojunction bipolar transistors (HBTs) under high self-heating operating conditions. The method uses three trivial DC measurements of the device where the junction temperature is known to be the same. This paper details the technique and applies it to both closely and widely spaced multi-finger HBT's, and compares the results to methods already known.

A 0.2-/spl mu/m 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Abstract: A technology for combining 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs) with CMOS transistors and high-quality passive elements has been developed for use in microwave wireless and optical communication systems. The technology has been applied to fabricate devices on a 200-mm SOI wafer based on a high-resistivity substrate (SOI/HRS). The fabrication process is almost completely compatible with the existing 0.2-/spl mu/m bipolar-CMOS process because of the essential similarity of the two processes. SiGe HBTs with shallow-trench isolations (STIs) and deep-trench isolations (DTIs) and Ti-salicide electrodes exhibited high-frequency and high-speed capabilities with an f/sub max/ of 180 GHz and an ECL-gate delay of 6.7 ps, along with good controllability and reliability and high yield. A high-breakdown-voltage HBT that could produce large output swings for the interface circuit was successfully added. CMOS devices (with gate lengths of 0.25 /spl mu/m for nMOS and 0.3 /spl mu/m for pMOS) exhibited excellent subthreshold slopes. Poly-Si resistors with a quasi-layer-by-layer structure had a low temperature coefficient. Varactors were constructed from the collector-base junctions of the SiGe HBTs. MIM capacitors were formed between the first and second metal layers by using plasma SiO/sub 2/ as an insulator. High-Q octagonal spiral inductors were fabricated by using a 3-/spl mu/m thick fourth metal layer.

GaN Electronics For High Power, High Temperature Applications

Abstract: A brief review is given of recent progress in fabrication of high voltage GaN and AlGaN rectifiers. GaN/AlGaN heterojunction bipolar transistors and GaN metal-oxide semiconductor field effect transistors. Improvements in epitaxial layer quality and in fabrication techniques have led to significant advances in device performance.

InP-InGaAs single HBT technology for photoreceiver OEIC's at 40 Gb/s and beyond

Abstract: We describe an advanced InP-InGaAs-based technology for the monolithic integration of pin-photodiodes and SHBT-transistors. Both devices are processed using the same epitaxial grown layer structure. Employing this technology, we have designed and fabricated two photoreceivers achieving transimpedance gains of 170 /spl Omega//380 /spl Omega/ and optical/electrical bandwidths of 50 GHz/34 GHz. To the best of our knowledge, this is the highest bandwidth of any heterojunction bipolar transistor (HBT)-based photoreceiver optoelectronic integrated circuit (OEIC) published to date. We even predict a bandwidth of 60 GHz for the same circuit topology by a simple reduction of the photodiode diameter and an adjustment of the feedback resistor value.

Linearity characteristics of GaAs HBTs and the influence of collector design

Abstract: The linearity characteristics of GaAs heterojunction bipolar transistors (HBTs) are studied through measurement and analysis. Third-order intermodulation distortion behavior of HBTs is examined on devices with various epilayer designs and at various bias points, loads, and frequencies. Calculations from an analytical model reveal a strong bias and load dependence of third-order intercept point (IP3) on the nonlinearities from transconductance and the voltage dependence of base-collector capacitance. However, a simple model is not able to predict the fine details of IP3 with bias. A large-signal HBT model with an accurate description of the base-collector charge is shown to account for the measured trends. The base-collector charge function accounts for the modulation of base-collector capacitance with current, electron velocity modulation, and the Kirk effect (base pushout) for GaAs-based HBTs. A detailed study of the influence of collector design on linearity is also presented.

Compact InP-based HBT VCOs with a wide tuning range at W- and D-band

Abstract: Compact monolithic integrated differential voltage-controlled oscillators (VCOs) operating in W-band were realized using InP-based heterojunction bipolar transistors (HBTs). The oscillators, with a total chip size of 0.6 by 0.35 mm/sup 2/, are based on a balanced Colpitts-type topology with a coplanar transmission-line resonator. By varying the voltage across the base-collector junction of the HBT in the current mirror and by changing the current in the VCO, the oscillation frequency can be tuned between 84 and 106 GHz. At 100 GHz, a differential voltage swing of 400 mV is obtained, which should be sufficient to drive 100 Gb/s digital logic. By combining the balanced outputs of a similar differential VCO in a push-push configuration, a compact source with close to -10 dBm output power and a tuning range between 138 and 150 GHz is obtained.

The values of minority carrier diffusion lengths and lifetimes in GaN and their implications for bipolar devices

Abstract: The wide bandgap semiconductors GaN and AlGaN show promise as the high voltage standoff layers in high power heterostructure bipolar transistors and thyristors due to their electric breakdown characteristics. Material properties which significantly influence the design and performance of these devices are electron and hole diffusion lengths and recombination lifetimes. We report direct measurements of minority carrier diffusion lengths for both holes and electrons by electron beam induced current. For planar Schottky diodes on unintentionally doped n-type and p-type GaN grown by metal organic vapor phase deposition (MOCVD), the diffusion lengths were found to be (0.28±0.03) μm for holes and (0.2±0.05) μm for electrons. Minority carrier lifetimes of approximately 7 ns for holes and 0.1 ns for electrons were estimated from these measured diffusion lengths and mobilities. In the case of GaN grown by halide vapor phase epitaxy (HVPE) diffusion lengths in the 1–2 μm range were found. We attempt to correlate the measured diffusion lengths and lifetimes with the structural properties of GaN and to explain why linear dislocations might act as a recombination centers. We calculate the performance of nitride based bipolar devices, in particular thyristor switches. The forward voltage drop across standoff layer of the nitride based thyristor switch is shown to significantly depend on the minority carrier (hole) lifetime.

Driving circuits for switch mode RF power amplifiers

Abstract: The present invention, generally speaking, provides an RF amplifier circuit architecture that enables high efficiency to be achieved while avoiding complicated matching networks and load networks The active device may be of the bipolar transistor type or the FET (field effect transistor) type A simple driving circuit is provided for each type of active device In accordance with one embodiment of the invention, a single-ended switch mode RF amplifier includes an RF input signal; an active device having a control terminal; and a non-resonant driving circuit for receiving the RF input signal and controlling a signal applied to the control terminal so as to operate the active device in switch mode

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

Abstract: An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation. Measurements and two-dimensional simulations are used to demonstrate that the graded-channel device efficiently alleviates the parasitic BJT action, improving the breakdown voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication factor and parasitic bipolar gain, which are the responsible parameters for the parasitic BJT action, are investigated separately providing a physical explanation. The abnormal subthreshold slope and hysteresis phenomenon are also studied and compared. (C) 2000 Elsevier Science Ltd. All rights reserved.

pn-junction delineation in Si devices using scanning capacitance spectroscopy

Abstract: The scanning capacitance microscope (SCM) is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope (SPM). As reported in Edwards et al. [Appl. Phys. Lett. 72, 698 (1998)], scanning capacitance spectroscopy (SCS) is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.

Method for novel SOI DRAM BICMOS NPN

Abstract: There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

Abstract: In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

Method for fabricating semiconductor device

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to obtain a high current gain by forming a logic CMOS, a high resisting pressure CMOS, and a bipolar transistor on the same substrate. CONSTITUTION: The first and the second conductive well regions are formed on the first conductive type substrate. A MOS transistor region(A,B), a high resisting pressure MOS transistor(C,D), and a bipolar transistor region(E,F) are defined. The first and the second insulating layers are formed on the semiconductor substrate. The first and the second layers are selectively removed. A field ion injection region(28) and a low density source/drain region(26,27) are formed on the MOS transistor region and a high resisting pressure MOS transistor. The first and the second conductive well regions and a base region are formed on the bipolar transistor region. A field oxide layer is formed on the MOS transistor region and the bipolar transistor region. A source/drain region is formed on the MOS transistor region and an emitter region(35) is formed on the bipolar transistor region.

Comparing SiC switching power devices: MOSFET, NPN transistor and GTO thyristor

Abstract: This paper for the first time systematically analyzed the operation mechanism of SiC NPN transistors. Theoretical device figure-of-merits for switching power devices based on the conduction loss and switching loss were developed. The on-state loss and the switching loss of 4.5-kV SiC switching power devices (MOSFET, NPN transistor and GTO thyristor) were then compared by using theoretical and numerical calculations. Special emphasis is placed on comparing the total power loss of the devices at a given current density. Theoretical analyses and simulation results show that GTO thyristors have a large switching loss due to the long current tail at turn-off, hence restricting its maximum operation frequency. High voltage SiC MOSFETs have a large on-state power dissipation at high current levels due to the resistive nature of the drift region, restricting their applications at high current densities. SiC NPN transistors have a comparable switching loss as that of SiC MOSFETs, but at the same time, SiC NPN transistors have the lowest on-state loss. This study indicates that SiC NPN transistor is the most attractive switching power device at 4.5 kV.

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, wherein the variation of the temp. characteristic of elements due to temp. gradient can be reduced. SOLUTION: This semiconductor integrated circuit 10 has a power transistor 11 disposed on it and has an npn transistor 12, a pnp transistor 13 and a pnp transistor 14 mounted on it. Each element 12, 13, 14 varies its characteristics with temp. and hence is disposed at an equal distance Z from the power transistor 11 and the elements 12-14 are covered with an Al wiring 15. If the pnp transistors 13, 14 form a differential amplifier circuit, the Al wiring 15 having thermal conductivity higher than the substrate is effective for reducing the characteristics variation due to temp. gradient and averaging the thermal distribution and of course improves the pair property of the pnp transistors 13, 14.

Threshold voltage generation circuit

Abstract: A threshold voltage generation circuit includes a control transistor, one or more load transistors, and a current mirror. The load transistors are diode-connected transistors that are operated in saturation. The source-to-gate voltage of the load transistors approximates the threshold voltage of the transistors over process and temperature. The operation of the circuit is affected by choosing a bias voltage for the control transistor, the sizes of the control transistor and load transistors, and the ratio of transistor sizes within the current mirror.

Bipolar transistor circuit analysis using the Lambert W-function

Abstract: The generalized diode equation describes conduction in a diode with series resistance. An analytical solution for the generalized diode equation has been elusive; however, one was found based on the transcendental equation w=ln(x/w). The solution of this equation; w=W(x), is traditionally referred to as the Lambert W-function. This function provides a long sought after natural continuity between exponential diode and linear resistor behavior. The W-function also describes more general circuits consisting of a diode or bipolar transistor with local linear negative or positive feedback. The properties of W(x) are reviewed and several iterative methods for its calculation are compared. Three approximations for the W function are derived which can simplify bipolar circuit analysis and design. The practical utility of the proposed solutions are demonstrated in four circuits along with experimental confirmation: a common emitter amplifier with an emitter or collector feedback resistor, Schmitt trigger threshold temperature compensation, bandgap stabilized current source, and a novel current-efficient laser driver.

Silicon: germanium-based mixed-signal technology for optimization of wired and wireless telecommunications

Abstract: The need to serve the explosion in data bandwidth demand for fixed and mobile applications has driven transistor performance requirements beyond the reach of conventional silicon devices. Scaling limits of silicon-based bipolar transistors have been encountered, confining further performance gains by traditional means, but cost considerations favor the continued use of silicon-derived technology solutions. Silicon: germanium (Si:Ge) heterojunction bipolar transistors (HBTs) and subsequent generations of highly integrated SiGe BiCMOS processes stem from long-term efforts initiated at IBM to develop such a silicon-derived technology. This paper reviews the application-driven origins of this SiGe technology, how it has evolved, and how limits to conventional silicon bipolar scaling have enhanced its adoption in the semiconductor industry. Examples of the entry of this technology into commercial applications in the wired and wireless marketplace are discussed.

Engineering the cascoded NMOS output buffer for maximum V/sub t1/

Abstract: The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.

Metamorphic InP/InGaAs double-heterojunction bipolar transistors on GaAs grown by molecular-beam epitaxy

Abstract: InP/InGaAs double-heterojunction bipolar transistor (HBT) structures were grown metamorphically on GaAs substrates by solid-source molecular-beam epitaxy. A linearly graded InxGa1−xP (x varying from 0.48 to 1) buffer layer was used to accommodate the strain relaxation. The crystallinity of the buffer layer and the HBT structure was examined by x-ray diffractometry. Devices with 5×5 μm2 emitter area showed a typical peak current gain of 40, a common-emitter breakdown voltage (BVCEO) higher than 9 V, a current gain cut-off frequency (fT) of 46 GHz, and a maximum oscillation frequency (fmax) of 40 GHz.

Perylene: A promising organic field-effect transistor material

Abstract: Field-effect transistors based on single crystalline perylene have been prepared and analyzed in the temperature range from 50 to 300 K Room temperature electron mobilities as high as 55 cm2/V s have been achieved In addition, ambipolar device operation, ie, n- and p-channel activity, is observed The temperature dependence of the electron and hole mobilities is discussed in the limits of hopping and band-like transport mechanisms

A solid state Marx type modulator for driving a TWT

Abstract: This paper describes a solid state Marx type modulator design delivering an 11 kilovolt, 2-4 /spl mu/sec pulse to the cathode of an X-band driver TWT. Insulated gate bipolar transistors (IGBTs) are used as on/off switches to operate the Marx circuit in the energy storage capacitor partial discharge mode. With the aid of a passive compensation circuit, a very flat TWT cathode driver pulse is obtained. The 2 /spl mu/sec, 11 kV pulse amplitude is flat to 0.06%.