Showing papers on "Decoupling capacitor published in 2001"

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Abstract: Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology

Abstract: Extended adaptive voltage positioning (EAVP) is a new robust methodology for the design and analysis of a low impedance resonant free power delivery network, which utilizes and extends the theory of adaptive voltage positioning (AVP) that is commonly used in voltage regulator module (VRM) design and operation. Using EAVP, uncertainties in design guardband noise budget can be removed, resulting in significant performance bin-split improvement and cost reduction. Design optimization of decoupling capacitors with EAVP will be illustrated by using both time and frequency domain analysis.

Liquid crystal display device, driving circuit, driving method, and electronic apparatus

Abstract: The voltage swing of a data signal, which is supplied to a data line, is maintained to be small, thereby reducing the power consumption. When a scanning signal supplied to a scanning line is set to an on-voltage, a data signal with a voltage, depending on the density and depending on the writing polarity, is applied to a data line. In this case, a TFT is turned on. Thus, a liquid crystal capacitor and storage capacitor store the charge corresponding to the voltage of the data signal. Then, the scanning signal is set to an off-voltage to turn the TFT off, and the voltage of the other terminal of the storage capacitor is raised from the low-level of capacitor voltage to the high-level, and the charge corresponding to the raised voltage amount is redistributed to the liquid crystal capacitor. Thus, the effective voltage value applied to the liquid crystal capacitor can correspond to the voltage swing of the data signal or more.

Analysis of power/ground-plane EMI decoupling performance using the partial-element equivalent circuit technique

Abstract: The design of printed circuit (PC) boards with decoupling capacitors has been the subject of debate and different opinions for many years. The design and electrical impact of the capacitors has been difficult to separate from all other electrical interactions occurring on a conventional PC board populated with integrated circuits. This work demonstrates how the partial-element equivalent circuit (PEEC) modeling technique can be used to accurately predict the performance of various decoupling design strategies. Computer modeling using the PEEC approach is very flexible due to the ease of mixing physical geometries with a large number of circuit elements. Also, the compute time for such practical mixed EM and circuit problems are relatively short. Using this technique, the usual iteration between a number of different designs of test boards can be avoided. We show that the change of the voltage across the PC board, or the voltage gradient, can be used as an effective tool for the improvement of the decoupling efficiency.

Design of planar integrated passive module for zero-voltage-switched asymmetrical half-bridge PWM converter

Abstract: Integrated L-L-C-T (inductor-inductor-capacitor-transformer) technology has been the subject of intensive research over the last few years. Its application to resonant power electronic converters has been reported by many previous publications. This paper presents the application of a planar L-L-C-T module to the integration of passive module for a zero-voltage-switched asymmetrical half bridge PWM converter for application in distributed power systems. Two output transformers, two current doubler inductors, the ZVS resonant inductor and the transformer DC decoupling capacitor are integrated into a single module. The design procedure is discussed and some special considerations of the L-L-C-T module in nonresonant applications are addressed. A 1 kW 300 V-400 V input, 48 V output asymmetrical half bridge PWM converter (AHBC) employing the L-L-C-T module is constructed. A comparison of the AHBC using the integrated passive module and the same circuit using discrete components is given.

Design of Planar Integrated Passive Module for Zero-Voltage Switched Asymmetrical Half Bridge PWM Converter

Abstract: Integrated L-L-C-T (inductor-inductor-capacitor-transformer) technology has been the subject of intensive research over the last few years. Its application to resonant power electronic converters has been reported by many previous publications. This paper presents the application of a planar L-L-C-T module to the integration of passive module for a zero-voltage-switched asymmetrical half bridge PWM converter for application in distributed power systems. Two output transformers, two current doubler inductors, the ZVS resonant inductor and the transformer DC decoupling capacitor are integrated into a single module. The design procedure is discussed and some special considerations of the L-L-C-T module in nonresonant applications are addressed. A 1 kW 300 V-400 V input, 48 V output asymmetrical half bridge PWM converter (AHBC) employing the L-L-C-T module is constructed. A comparison of the AHBC using the integrated passive module and the same circuit using discrete components is given.

Low inductance four terminal capacitor lead frame

Abstract: A chip capacitor is conductively coupled to spaced-apart (ie, non-conductively coupled) circuit traces of an integrated circuit to provide a four terminal network The chip capacitor includes a casing of dielectric material having first and second sets of electrode plates disposed therein, a first conductive lead frame which is conductively coupled to the first set of electrode plates, and a second conductive lead frame which is conductively coupled to the second set of electrode plates The first and second lead frames are, in turn, conductively coupled to the circuit traces so as to route the output (or input) current of an electronic device through the capacitor

The carrier-based PWM method for voltage balance of flying capacitor multilevel inverter

Abstract: This paper proposes a new solution using a carrier-based PWM method to solve the most serious problem of flying capacitor multi-level inverters, that is the unbalance of capacitor voltages. The voltage unbalance occurs due to the difference of each capacitor's charging and discharging time applied to the flying capacitor inverter. The new solution controls the variation of capacitor voltages into the mean '0' during some period by means of new carriers using the leg voltage redundancy in the flying capacitor inverter. The solution can be easily expanded to multi-level inverters. Also, this method can make the switching loss and conduction loss of devices equal by the use of leg voltage redundancy. First, this paper examines the unbalance of capacitor voltage and the conventional theory of self-balance using phase-shifted carriers. Then, a new method that is suitable for flying capacitor inverters is explained. Simulation results verify the proposed method.

Transient analysis of a unified power flow controller and its application to design of the DC-link capacitor

Abstract: This paper presents a transient analysis of a unified power flow controller (UPFC), and design of capacitance of the DC-link capacitor. Active power flowing out of the series device in transient states is theoretically discussed to derive what amount of electric energy the DC link capacitor absorbs or releases through the series device. As a result, it is clarified that the active power flowing out of the series device is stored in the line inductance as magnetic energy during transient states. Design of capacitance of the DC-link capacitor is also presented in this paper, based on the theoretical analysis. Experimental results obtained from a 10-kVA laboratory setup are shown to verify the analytical results.

On the Circuit Model of Piezoceramics

Abstract: The proper equivalent interface circuit of a piezoelectric material below ultrasonic frequency range is developed and analyzed incorporating a voltage source and a capacitor theoretically and experimentally. The emphasis is placed on the physical connection between a capacitor and a voltage source. The first model considered is of a capacitor connected in series with a voltage source. The second model consists of a capacitor connected in parallel with a voltage source. This paper presents the analyses of these two different circuit models for a piezoceramic by discussing the electric impedance and phase angle of a piezoceramic theoretically and experimentally and determines the best-fit model of a PZT to use for structural vibration applications.

IC power distribution challenges

Abstract: With each technology generation, delivering a timevarying current with reduced nominal supply voltage variation is becoming more difficult due to increasing current and power requirements. The power delivery network design becomes much more complex and requires accurate analysis and optimizations at all levels of abstraction in order to meet the specifications. In this paper, we describe techniques for estimation of the supply voltage variations that can be used in the design of the power delivery network. We also describe the decoupling capacitor hierarchy that provides a low impedance to the increasing high-frequency current demand and limits the supply voltage variations. Techniques for high-level power estimation that can be used for performance vs. power trade-offs to reduce the current and power requirements of the circuit are also presented.

Transmitter system for wireless communication with implanted devices

Abstract: A transmitter system for wireless communication with implanted medical devices includes a transmitter circuit having a resonant network the resonant frequency of which is adjusted by a feedback circuit in order to minimize the current drain from the power source and maximizing the power source life. The transmitter system may be powered by a power supply block which uses commonly available RS-232 signals of a host computer as a raw power source, combined with a high value storage capacitor to provide power for the wireless medical data programmer. A feedback circuit monitors the charging current as well as voltage impressed across the storage capacitor in order to maintain the charging current at maximum level during the charging time and in order to stop the charging once the full charge of the storage capacitor has been reached.

Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Power-supply decoupling on fully populated high-speed digital PCBs

Abstract: The effectiveness of buried capacitance technology, used with discrete surface mounted decoupling capacitors, in reducing circuit malfunctions due to the noise voltage between power/ground planes in a multilayer printed circuit board is investigated. The analysis is carried out on a fully populated multilayer board, where an integrated circuit with very large package provides a lot of digital signals with measured rise/fall times equal to 400 ps. The role of the integrated circuit's package in damping out the resonance peaks at resonance frequencies on the power plane is highlighted. The relations between the power-bus transfer impedance and noise spectrum are also studied, in order to better evaluate the effects of the buried capacitance technology and decoupling capacitors on the power-bus noise filtering.

Multiplex voltage measurement apparatus

Abstract: A multiplex voltage measurement apparatus includes: (N+1) voltage detection terminals connected to N serially connected voltage sources; a capacitor which is charged with a voltage value of any of the N voltage sources; a first sample switch for selectively connecting odd-numbered voltage detection terminals among the (N+1) voltage detection terminals to a first terminal of the capacitor; a second sample switch for selectively connecting even-numbered voltage detection terminals among the (N+1) voltage detection terminals to a second terminal of the capacitor; a voltage measurement circuit for measuring the voltage value stored in the capacitor; a third sample switch for connecting the first terminal and the second terminal of the capacitor to the voltage measurement circuit; and a polarity controller for controlling the first and second sample switches such that one of the N voltage sources is selected while the third sample switch is open.

Integrated high-performance decoupling capacitor and heat sink

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

A novel capacitance control design of tunable capacitor using multiple electrostatic driving electrodes

Abstract: A novel method that is capable of linearly electrostatic driving a tunable capacitor is proposed in this paper. By extending the derivation of electrostatic theory and elastic theory in constructing the tunable capacitor, the nonlinear relationship between applied voltages and displacement (air gap) between two parallel plates of the capacitor is obtained. To suppress the nonlinearity so that the gap between the capacitor can vary linearly with the applied voltage, a control design method based on the variation of the multi-rectangular electrodes and applied voltages is proposed. By varying the number of rectangular electrodes that are evenly divided according to the size of the upper plate of the capacitor, the working space of the tunable capacitor with nonlinear characteristics is obtained. With this working space, linear control design method based on fixed or linearly varied applied voltages can be used to determine the number of the multi-rectangular electrodes such that stepping effect of the tunable capacitor can be achieved. Examples are used to demonstrate the feasibility of the present control design.

Multiple port bi-directional power converter

Abstract: In one embodiment of the present invention, a bi-directional power converter is described. The converter comprises a first bi-directional DC-DC conversion device having a first plurality of bi-directional DC-DC converters, a plurality of power supply ports, each connected to at least one of the first plurality of bi-directional DC-DC converters, and a voltage medium capacitor, which is connected to each of the first plurality of bi-directional DC-DC converters and has a first voltage greater than a second voltage measured at each of the power supply ports. The converter further may comprise a third bi-directional DC-DC converter device, which is connected to the voltage medium capacitor and is connected to a voltage high capacitor. The converter also may comprise a bi-directional AC-DC conversion device, which bi-directional AC-DC conversion device is connected to the voltage high capacitor and at least one inductor, which is connected to a plurality of AC ports. In another embodiment of the present invention, at least one of the DC ports may be a hydrogen fuel cell.

Decoupling capacitance allocation for power supply noise suppression

Abstract: We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on the power supply noise estimates. A linear programming technique is used to maximize the allocation of the existing white space in the floorplan for the placement of decoupling capacitors. An incremental heuristic is proposed to insert more white space into the existing floorplan to meet the remaining demand required for decoupling capacitance fabrication. Experimental results on six MCNC benchmark circuits show that the white space allocated for decoupling capacitance is about 6%-12% of the chip area for the 0.25mm technology, and the power supply noise can be kept below 10%Vdd.

MEMS variable capacitor with stabilized electrostatic drive and method therefor

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver ( 120 ) having a driver capacitor of fixed capacitance ( 121 ) in series with a second driver capacitor of variable capacitance ( 126 ). A MEMS variable capacitor ( 130 ) is controlled by applying an actuation voltage potential to the electrostatic driver ( 120 ). The electrostatic driver ( 120 ) and MEMS variable capacitor ( 130 ) are integrated in a single, monolithic device.

Integrated decoupling capacitors

Abstract: A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.

Electrical behavior of decoupling capacitors embedded in multilayered PCBs

Abstract: We describe the modeling of prototype capacitors embedded in multilayered printed circuit boards. We present the design of these devices. We also report measurement and characterization results. The emphasis is on the modeling of via hole connections to the embedded capacitor, not on the technology of buried capacitors. Several designs have been compared with respect to their electrical behavior. In particular, several via hole configurations have been studied, because they are the main cause of parasitic behavior. With these buried capacitors, we obtained a reduction of the parasitic inductance of 80% compared to an equivalent discrete capacitor. This work has been carried out under a European Brite-EuRAM funded project COMPRISE (BE 96-3371). The objective of this project was to develop new materials and manufacturing processes to embed passive components (R, L, and C) within printed wiring structures fabricated from laminate materials. This technology enables the manufacture of space efficient and radio frequency (RF) optimal performing types of modules or board assemblies particularly suited to the market domain of portable and handheld communication and information technology products.

DC power-bus design using FDTD modeling with dispersive media and surface mount technology components

Abstract: DC power-bus modeling in high-speed digital design using the finite-difference time-domain (FDTD) method is demonstrated herein. The dispersive character of the dielectric layers used in printed circuit board substrates is taken into account in this study. In particular, FR-4 is considered. The complex permittivity of the dielectric is approximated by a Debye model. A wide-band frequency response (100 MHz-5 GHz) is obtained through a single FDTD simulation. Good agreement is achieved between the modeled and measured results for a typical dc power-bus structure with multiple surface mount technology (SMT) decoupling capacitors placed on the printed circuit board (PCB). The FDTD method is then applied to investigate some general approaches of power-bus noise decoupling.

Battery monitoring system for an implantable medical device

Abstract: An implantable cardiac device, such as a pacemaker, provided with a carbon monofluoride (CF x ) battery. The CF x battery enables replacement of the typical voltage tripler with a voltage doubler and eliminates the need for a bulky decoupling capacitor. The device includes a precision A/D and voltage monitor to enable more accurate prediction of impending battery end-of-life. Several methods of accurately determining a pending end-of-life of a battery with a flat voltage output throughout discharge, such as a CF x battery, are provided.

Switching regulator for implantable spinal cord stimulation

Abstract: An improved switching regulator for implantable medical devices includes a control circuit with a capacitor divider to conserve energy, and selectable duty cycles to efficiently match the duty cycle to the charge level in a holding capacitor. The switching regulator charges the holding capacitor to commanded voltage levels, and the holding capacitor provides current for tissue stimulation. The commanded voltage level is reached by “pumping-up” the holding capacitor with the output of the switching regulator. For control purposes, the high voltage (i.e., the voltage across the holding capacitor) is divided between a fixed capacitor and a variable capacitor, and the voltage between the fixed capacitor and the variable capacitor (i.e., the divided voltage) is compared to a reference voltage. The result of the comparison is used to turn-off the switching regulator once the commanded voltage level is reached. The switching duty cycle is set to one of two values. At start-up, or when the output voltage drops below a determined threshold, a low duty cycle is used. Once the output voltage reaches the threshold, a higher duty cycle is used.

Comparative evaluation of modulation methods for a three-phase/switch buck power factor corrector concerning the input capacitor voltage ripple

Abstract: For a three-phase three-switch buck-type PWM rectifier with unity power factor, the RMS value of the input filter capacitor voltage ripple is calculated for different modulation methods. A modulation method being optimal concerning the occurring switching losses and the RMS value of the capacitor voltage ripple is identified and guidelines for the dimensioning of the input filter are derived.

Flying capacitor battery pack voltage detecting circuit and driving method for it

Abstract: PROBLEM TO BE SOLVED: To provide a flying capacitor voltage detecting circuit capable of reducing power consumption and detecting a disconnection failure. SOLUTION: In the flying capacitor battery pack voltage detecting circuit, a reset switch SW1 is turned on to reset a flying capacitor 3, and then according to the read out voltage of a voltage module, disconnection failure of a multiplexer 2 is determined. COPYRIGHT: (C)2003,JPO

Simultaneous switching noise suppression for high speed systems using embedded decoupling

Abstract: High performance computing systems are driving towards higher clock speeds, more switching circuits, and lower operating voltages. Simultaneous switching noise (SSN) will greatly affect signal integrity in such complex future mixed signal systems. It has been reported that in addition to inductance effects, power plane bounce also becomes a critical factor for packages containing many power and ground vias in parallel. Discrete surface mount capacitors are currently being used by designers to suppress noise. As part of the System on a Package (SOP) concept being developed at the Packaging Research Center (PRC), Georgia Tech, a test vehicle to demonstrate the suppression of SSN using embedded decoupling capacitors is being implemented. This test vehicle uses thin film sequential buildup technology on a low-cost organic platform incorporating polymer-ceramic nanocomposite dielectrics. The design rules for the test vehicle were developed using SOP substrate materials and processes; furthermore, Ansoft along with Matlab were used to model the microstrip transmission lines. The layout was done using Cadence Advanced Package Designer (APD) and output into Gerber format for fabrication. The current test vehicle uses a 300 mm /spl times/300 mm high T/sub g/ FR-5 base substrate with four metal layers on each side. Photoimageable epoxy dry films of 25 /spl mu/m and 75 /spl mu/m thickness were used as the low k (3.4-3.9) sequential build-up dielectric. A novel photoimageable polymer ceramic nanocomposite material developed at the PRC was used for the high k (25-50) thin films. Low cost materials and large area processes were used for the substrate fabrication including dry film printed wiring board (PWB) photoresists, vacuum lamination and spin/meniscus coating for dielectric deposition, full-field UV lithography, and electroless and electrolytic copper metallization. Simulations confirm that the SSN will be suppressed by a factor often when using the high k material as the capacitor dielectric. This paper presents the design, fabrication and validation of embedded decoupling for SOP technology.

Voltage clamping system and method for a dc/dc power converter

Abstract: A voltage boost power converter circuit, having an input inductor, active switch, and a transformer having primary, secondary and auxiliary windings A clamping capacitor and a first passive switch are in series across the primary winding The auxiliary winding and a second passive switch are in series, connected to the node between the clamping capacitor and first passive switch The active switch is connected between ground the primary winding A bulk capacitor forms a series loop including the active switch and primary winding The method efficiently resets a the transformer, by transferring power to a load through the primary winding, and discharging a clamping capacitor through a separate inductively linked winding of the transformer during an ON state; and clamping the active switch voltage with the clamping capacitor, charging the clamping capacitor with a leakage inductance of the transformer, and charging the bulk capacitor during an OFF state

Circuit board capacitor structure for forming a high voltage isolation barrier

Abstract: A circuit board capacitor structure operable as a high voltage isolation barrier in communication circuitry. Capacitor electrodes form a capacitive structure directly on a printed circuit board's opposing sides. The PCB substrate intermediate the electrodes functions as the capacitive structure's dielectric material. The capacitor electrodes are sized such that the electrodes' area and the substrate's dielectric properties create the desired capacitance. Alternatively, a multi-layered PCB may be utilized where layer(s) is/are used to form the capacitive structure. The circuit board capacitor may couple communication circuitry located on the PCB's various sides. The circuit board capacitor operates as a high voltage isolation barrier in data access arrangements, separating line and system side circuitry. Further, the high voltage isolation barrier may include multiple circuit board capacitors to realize differential communications and/or multiple datapaths. The capacitor structure can be flexibly arranged to minimize PCB real estate and be more cost-effective than discrete capacitors.