Showing papers on "Electronic packaging published in 2000"

Electronic Packaging and Interconnection Handbook

Abstract: Table of contents CONTRIBUTORS PREFACE Chapter 1: Plastics, Elastomers, and Composites Chapter 2: Adhesives, Underfills, and Coatings Chapter 3: Thermal Management Chapter 4: Connector and Interconnection Technology Chapter 5: Solder Technologies for Electronic Packaging and Assembly Chapter 6: Packaging and Interconnection of Integrated Circuits Chapter 7: Hybrid Microelectronics and Multichip Modules Chapter 8: Chip Scale, Flip Chip, and Advanced Chip Packaging Technologies Chapter 9: Rigid and Flexible Printed Circuit Board Technology Chapter 10: Packaging of High-Speed and Microwave Electronic Systems INDEX

Atomic layer controlled deposition on particle surfaces

Abstract: Particles have an ultrathin, conformal coating are made using atomic layer deposition methods. The base particles include ceramic and metallic materials. The coatings can also be ceramic or metal materials that can be deposited in a binary reaction sequence. The coated particles are useful as fillers for electronic packaging applications, for making ceramic or cermet parts, as supported catalysts, as well as other applications.

Thermal Design of Electronic Equipment

Abstract: Thermal design of electronic equipment , Thermal design of electronic equipment , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Hermeticity of electronic packages

Abstract: Hermeticity of electronic packages , Hermeticity of electronic packages , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Challenges in interconnection and packaging of microelectromechanical systems (MEMS)

Abstract: Integrated circuit packaging and their testing is well advanced because of the maturity of the IC industry, their wide applications, and availability of industrial infrastructure. This is not true for MEMS with respect to packaging and testing. It is more difficult to adopt standardized MEMS device packaging for wide applications although MEMS use many similar technologies to IC packaging. Packaging of MEMS devices is more complex since in some cases it needs to provide protection from the environment while in some cases allowing access to the environment to measure or affect the desired physical or chemical parameters. Microscopic mechanical moving parts of MEMS have also their unique issues. Therefore, testing MEMS packages using the same methodologies, as those for electronics packages with standard procedures might not always be possible especially when quality and reliability need to be assessed. Single MEMS chip packaging approaches and their limitations in the packaging of high performance MEMS will be reviewed in this presentation and also identifies a need for a systematic approach for this purpose. MEMS package reliability depends on package type, i.e. ceramic, plastic, or metal, and reliability of device. The MEMS device reliability depends on its materials and wafer level processes and sealing methods used for environmental protection. MEMS quality and reliability challenges are discussed and needs for study in these areas are identified.

Flip the Chip

Abstract: As integrated circuit fabrication advances rapidly and the market for faster, lighter, smaller, yet less expensive electronic products accelerates, electronic packaging faces its own challenges. In this Perspective, Wong, Luo, and Zhang describe recent advances in flip chip packaging. This technology has many advantages over the conventional wire bonding technology and offers the possibility of low-cost electronic assembly for modern electronic products.

An embedded overlay concept for microsystems packaging

Abstract: An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.

Electrical and fluidic packaging of surface micromachined electromicrofluidic devices

Abstract: Microfluidic devices have applications in chemical analysis, biomedical devices and ink-jets1. An integrated microfluidic system incorporates electrical signals on-chip. Such electro-microfluidic devices require fluidic and electrical connection to larger packages. Therefore electrical and fluidic packaging of electro-microfluidic devices is the key to the development of integrated microfluidic systems. Packaging is more challenging for surface micromachined devices than for larger bulk micromachined devices. However, because surface micromachining allows incorporation of electrical traces during microfluidic channel fabrication, a monolithic device results. A new architecture for packaging surface micromachined electro- microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macroscale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors. The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch2 etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Adhesion measurement for electronic packaging applications using double cantilever beam method

Abstract: Multilayers and interfaces are ubiquitous in microelectronics devices, interconnect and packaging structures. As the interface integrity becomes the major concern of performance, yield, and reliability, the need to evaluate the fracture and delamination behavior of various interfaces increases. This work focused on quantifying interfacial adhesion performance of a typical electronics packaging structure, flip-chip-on-organic-substrate. A series of experiments and analyzes were conducted to investigate the adhesion and fracture behaviors of the underfill/silicon and underfill/organic substrate interfaces. The experimental techniques for the interfacial fracture experiments were developed to produce the double-cantilever-beam (DCB) specimens and to establish a reproducible testing protocol. To extract the interfacial fracture energies, a closed-form solution was developed based on a beam-on-elastic-foundation model. A two-dimensional elastoplastic finite element analysis (FEA) model was also implemented to examine effects of mode-mixity, thermal/residual stresses, and underfill plasticity. The techniques allow for reproducible determination of underfill/printed circuit board (PCB) and underfill/silicon chip interfacial adhesion strength. The developed techniques are also readily applicable to evaluate interfacial adhesion performance for many other similar electronic packaging systems. This provides capabilities in optimizing material selections and process conditions to improve interfacial adhesion performance, Additionally, the interfacial fracture energy measured with high accuracy can provide a basis for realistic modeling of thermo-mechanical reliability of electronic components.

Feasibility of surface activated bonding for ultra-fine pitch interconnection-a new concept of bump-less direct bonding for system level packaging

Abstract: In the present study a method of ultra-high density interconnection, the surface activation (SAB) method is introduced. Also for the next generation of packaging, which might bridge to global interconnection on chip, a concept of bump-less bonding is proposed. The bumpless bonding will be especially suitable and inevitable for ultra-high density interconnection when it will convert the range of /spl mu/m size. For such bonding requires at the same time, combinations of a ultra-thin chip and a flexible substrate. The surface activated bonding method enables the metals and non-metallic materials to be bonded at room temperature only by contact. Some fundamental experiments and preliminary results of examination of the feasibility of the method for Cu and Cu direct bonding are presented.

Application of the Taguchi method to chip scale package (CSP) design

Abstract: A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS/sup TM/ finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L/sub 18/ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125/spl deg/C to -40/spl deg/C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125/spl deg/C to -40/spl deg/C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25/spl deg/C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls.

Ultrathin wafer level chip size package

Abstract: The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment Dies are packaged and encapsulated into separate enclosures while still in wafer form This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection A proprietary compliant polymer layer under the bumps provides on board reliability Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards Such chip scale packages (CSP's) measure 300-700 /spl mu/m in thickness, a crucial factor for use in various size sensitive electronic products

Ultrathin wafer level chip size package

Abstract: The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with joint electron device engineering council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products.

Comparative study of micro-BGA reliability under bending stress

Abstract: The micro-ball grid array (/spl mu/BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by ordinary surface mount technology. In the latest /spl mu/BGA type, eutectic tin-lead solder ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the /spl mu/BGA's PCB, which is soldered by conventional surface mount technology, has been studied in this paper. The bending cycle test (1000 /spl mu//spl epsi/ to -1000 /spl mu//spl epsi/), is used to investigate the fatigue failure of solder joints of /spl mu/BGA, PBGA, and CBGA packages reflowed with different heating factors (Q/sub /spl eta//), defined as the integral of the measured temperature over the dwell time above liquidus (183/spl deg/C). The fatigue lifetime of the /spl mu/BGA assemblies firstly increases and then decreases with increasing heating factor. The greatest lifetime happens while Q/sub /spl eta// is near 500 second-degree. The optimal Q/sub n/ range is between 300 and 750 s/spl deg/C. In this range, the lifetime of the /spl mu/BGA assembly is greater than 4500 cycles if the assemblies are reflowed in nitrogen ambient. SEM micrographs reveal that both /spl mu/ & P-BGA assemblies fail in the solder joint at all heating factors. All fractures are near and parallel to the PCB pad. In the /spl mu/BGA assemblies cracks always initiate at the point of the acute angle where the solder joint joins the PCB pad, and then propagate in the section between the Ni/sub 3/Sn/sub 4/ intermetallic compound (IMC) layer and the bulk solder. In the CBGA assembly reliability test, the failures are in the form of delamination, at the interface between the ceramic base and metallization pad.

Chip-scale packaging of power devices and its application in integrated power electronics modules

Abstract: A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D/sup 2/BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D/sup 2/BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V/sub CE/(sat) and on-resistance of the D/sup 2/BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D/sup 2/BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.

Packaging design of microsystems and meso-scale devices

Abstract: This paper will present an overview on electromechanical packaging of microelectromechanical systems (MEMS) and microsystems such as microsensors, actuators, and fluidics. Technical problems and major issues related to packaging design will also be presented and discussed.

Mechanical characterization of plastic ball grid array package flexure using moire interferometry

Abstract: Most previous studies of PBGA packaging reliability focused on the effect of thermal cycling. However, as portable electronic products such as cellular phones and laptop computers are reduced in size and become more readily available, isothermal flexural fatigue also becomes an important reliability issue. Solder interconnects subjected to mechanically induced deformation may result in failure. In the current work, moire interferometry is used to investigate the influence of PCB flexure on interconnect strains. A versatile testing apparatus is developed to load PBGA packages in four point bending. Moire fringe patterns are recorded and analyzed at various bending loads to examine the variation in displacement and strain between the components. Solder balls across the entire array experience large shear strains, often resulting in plastic deformation, which reduces service life of the package.

A heat spreading resistance model for anisotropic thermal conductivity materials in electronic packaging

Abstract: The electronic package structure often comprises of materials that occur in thin layers In many instances, these materials are lumped Together as a simplified compact model to represent their thermal performance enabling parametric studies of the package structure This new compact structure will have a new set of thermal properties that differs from its constituent components Their combined material properties often display anisotropic thermal conductivity because layers of conductive and less conductive materials results in an orthogonal heat transfer behavior This paper addresses the analytical and numerical studies of heat spreading in an anisotropic conductivity material with particular reference to the printed circuit boards (PCB) The PCB is considered to be a single material with highly anisotropic thermal conductivity, depending on the distribution of copper planes and thermal vias The motivation for this study is to determine an appropriate anisotropic spreading resistance formulation that can be used in compact models of electronic packages

Ultra CSP/sup TM/-a wafer level package

Abstract: There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP/sup TM/. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed.

Power electronics technology at the dawn of a new century-past achievements and future expectations

Abstract: The paper examines the present power electronics technology in terms of its constituent technologies. The present trends are discussed. Packaging as a central driver is evaluated and the necessity for a paradigm shift in power electronics technology identified. Future possibilities in terms of integration and packaging of all active and passive functions into a hybrid module are discussed and concluded with an exposition of a wide ranging research program to develop future technology.

Microrelay packaging technology using flip-chip assembly

Abstract: Using flip-chip assembly, micromachined connectors can be used to create a high density, actuatable electronics packaging technology. Internal residual stress is used to press bimorph beam connectors upwards against a device chip. Deformation can be increased by introducing stress through a heat treating process. The effects of heat treatment are more prominent on larger devices and are long lasting in nature. The connectors' actuation behavior is described, including appropriate mathematical models. The electrostatically actuated beams will disconnect when driven by a 53 volt signal and will reconnect when voltage falls below 43 volts. When switching signals, reconnection occurs in as little as 5.8 /spl mu/s, disconnection occurs in as little as 4.0 /spl mu/s. A microconnector's current carrying capability can be as high as 285.3 mA and its maximum power dissipation as high as 1.47 W.

Wafer-level chip scale packaging: benefits for integrated passive devices

Abstract: Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with "fine pitch BGA" as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost.

Free-space parallel multichip interconnection system

Abstract: A parallel data-communication scheme is described for interchip communication with free-space optics. We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM). Our packaging architecture is based on a modified folded 4-f imaging system that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built, supports 48 independent free-space channels with eight separate laser and detector chips, in which each chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic (OE) free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact at only 10 in.3 (∼164 cm3) and is scalable because it can easily accommodate additional chips as well as two-dimensional OE device arrays for increased interconnection density.

Trends in electronic packaging and assembly for portable consumer products

Abstract: In this paper, an overview is given of trends in electronic packaging and assembly for portable consumer products. With regard to components, the focus is on thinner and smaller packages with a higher lead count. To save board space, integrated passive components in CSP format are being developed. The use of modules that provide a complete function is increasing. Advantages are flexibility, diversity, and cheaper and simpler second-level assembly (the high-density interconnect is limited to the interior of the module). Both motherboards and interposer substrates (used in packages and modules) are characterised by smaller features to accommodate higher I/O density, and reduced thickness to limit the overall electronic assembly height. For the same reasons, techniques and materials have been developed to enable embedded passives. New substrate materials have been developed with better electrical and thermal behaviour to comply with RF requirements. In assembly processes, package assembly is done increasingly at wafer or substrate level to save costs, increase production volume, and facilitate package miniaturisation. Standard reflow soldering is optimised to enable the integration of CSPs and flip-chips on the motherboard. In some areas, conductive adhesive is used, e.g. to get smaller bump pitches on flip-chips. Finally, due to market demand and legislation, assembly processes, components, and materials must be adapted to realise environmentally friendly products. Special attention is paid to the elimination of lead, volatile organic compounds, and halogens.

Ultra-thin composite surface finish for electronic packaging

Abstract: In accordance with the invention, a packaged electronic device comprises at least one electronic device and leads sealed within a protective package. The leads comprise a conductive metal substrate having a composite metal finish with a total thickness of 1000 Å or less. The finish comprises, in succession from the substrate, 25-750 Å of palladium alloy and 5-250 Å of wirebondable and solderable material. The substrate is advantageously nickel-plated copper alloy or Fe—Ni alloy. The content of palladium in the palladium alloy coating can range from 10-95 weight percent. This finish meets requirements of wirebonding and solderability at a thickness surprisingly lower than previously used packaging finishes.