scispace - formally typeset
Search or ask a question

Showing papers on "Isotropic etching published in 1993"


Journal ArticleDOI
TL;DR: In this paper, a technique for patterning a self-assembled monolayer (SAM) on a gold substrate using an elastomer stamp was described, followed by selective etching in an aqueous, basic solution of cyanide ion and dissolved dioxygen (1M KOH, 0.1 M KCN).
Abstract: This letter describes a technique that can be used to produce well‐defined features of gold. The technique involves patterning of a self‐assembled monolayer (SAM) on a gold substrate using an elastomer stamp (fabricated either from a phenol‐formaldehyde polymer or polydimethylsiloxane), followed by selective etching in an aqueous, basic solution of cyanide ion and dissolved dioxygen (1M KOH, 0.1 M KCN). Electrically conductive structures of gold with dimensions as small as 1 μm have been produced using this procedure. Once a rubber stamp is fabricated, patterning and etching of gold substrates is straightforward. This method is convenient, does not require routine access to clean rooms and photolithographic equipment, and can be used to produce multiple copies of a pattern.

1,756 citations


Patent
Franz Laermer1, Andrea Schilp1
27 Nov 1993
TL;DR: In this paper, anisotropic plasma etching of silicon is used to provide laterally defined recess structures therein through an etching mask employing a plasma, the method including anisotropically-plasmine etching, polymerizing in a polymerizing step at least one polymer former contained in the plasma onto the surface of the silicon during which the surfaces that were exposed in a preceding etching step are covered by a polymer layer thereby forming a temporary etching stop.
Abstract: A method of anisotropic plasma etching of silicon to provide laterally defined recess structures therein through an etching mask employing a plasma, the method including anisotropic plasma etching in an etching step a surface of the silicon by contact with a reactive etching gas to removed material from the surface of the silicon and provide exposed surfaces; polymerizing in a polymerizing step at least one polymer former contained in the plasma onto the surface of the silicon during which the surfaces that were exposed in a preceding etching step are covered by a polymer layer thereby forming a temporary etching stop; and alternatingly repeating the etching step and the polymerizing step. The method provides a high mask selectivity simultaneous with a very high anisotropy of the etched structures.

934 citations


Journal ArticleDOI
G. A. C. M. Spierings1
TL;DR: The etch rate is determined by the composition of the etchant as well as by the glass, although the mechanism of dissolution is not influenced as discussed by the authors, since the dissolution reaction is governed by the adsorption of the two reactive species: HF and HF 2 - and the catalytic action of H+ ions.
Abstract: The etching of silicate glasses in aqueous hydrofluoric acid solutions is applied in many technological fields. In this review most of the aspects of the wet chemical etching process of silicate glasses are discussed. The mechanism of the dissolution reaction is governed by the adsorption of the two reactive species: HF and HF 2 - and the catalytic action of H+ ions, resulting in the breakage of the siloxane bonds in the silicate network. The etch rate is determined by the composition of the etchant as well as by the glass, although the mechanism of dissolution is not influenced. In the second part of this review, diverse applications of etching glass objects in technology are described. Etching of SiO2 and doped SiO2 thin films, studied extensively for integrated circuit technology, is discussed separately.

371 citations


Patent
03 Dec 1993
TL;DR: In this paper, a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation is described.
Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

208 citations


Patent
Kouhei Kawamura1
25 Mar 1993
TL;DR: An NF 3 /H 2 mixture as a feed gas for an etchant for etching an SiO 2 film on an silicon wafer is used with a 1 : 160 NF 3/H 2 mixed ratio.
Abstract: An NF 3 /H 2 mixture as a feed gas for an etchant for etching an SiO 2 film on an silicon wafer is used with a 1 : 160 NF 3 /H 2 mixed ratio. The mixture is made into plasma, and activated species of fluorine, hydrogen and nitrogen are supplied downstream to allow the species to be adsorbed in and on the SiO 2 film. The NF 3 /H 2 mixed ratio of the mixture is so set as not to effect the etching of the SiO 2 film under a chemical action. Then the adsorbed activated species are irradiated with Ar low energy ions so that the activated species are excited and etch the SiO 2 film. During etching, the semiconductor wafer is maintained to about -100° C. Less damage is caused to the silicon wafer and etching can be made in a high selection ratio.

192 citations


Journal ArticleDOI
TL;DR: In this article, a self-assembled monolayer of n−octadecanethiol (C18H37SH) was used as a mask for chemical etching of GaAs.
Abstract: We present results on electron beam exposure of a self‐assembled monolayer film as a self‐developing positive resist on GaAs. A 1.5 nm thick monolayer of n‐octadecanethiol (C18H37SH) deposited on a GaAs (100) substrate showed a electron beam sensitivity of about 100 μC/cm2. The monolayer resist was used as a mask for chemical etching of the GaAs. Patterns in GaAs have been created with widths approximately equal to the exposing electron beam width of 50 nm.

156 citations


Journal ArticleDOI
TL;DR: In this article, a technique for fabricating Si nanostructures with a scanning tunneling microscope operated in air is presented, which involves direct chemical modification of a H-passivated Si(100) surface and a subsequent liquid etch.
Abstract: A technique is presented for fabricating Si nanostructures with a scanning tunneling microscope operated in air. The process involves the direct chemical modification of a H‐passivated Si(100) surface and a subsequent liquid etch. The chemically modified portions of the surface can withstand a deep (≳100 nm) liquid etch of the unmodified regions with no etch degradation of the modified surface. At a write speed of 1–10 μm/s, large‐area (50 μm×50 μm) patterns with lateral feature sizes ∼25 nm are reliably fabricated.

151 citations


Journal ArticleDOI
TL;DR: In this article, damage-free selective etching of Si native oxides against Si has been achieved by NH3/NF3 and SF6/H2O downflow etching.
Abstract: Damage‐free selective etching of Si native oxides against Si has been achieved by NH3/NF3 and SF6/H2O down‐flow etching. In the NH3/NF3 etching, the wafer was covered with a film, and after its removal by heating above 100 °C, only SiO2 was found to be etched with an extremely high selectivity with respect to Si. Selective etching of Si oxides has also been obtained for SF6/H2O microwave discharge. In this case, a film of liquid solution containing HF and H2SOx is considered to form on the wafer surface. The selective etching of SiO2 takes place by the dissolved HF just as in the wet etching by an HF solution. The mechanisms of these selective reactions are discussed in detail based on the covalency of Si and SiO2 bondings.

137 citations


Journal ArticleDOI
TL;DR: An etching mechanism for thin silicon dioxide films in hydrofluoric acid solutions has been deduced from experimental results and a review of literature sources as mentioned in this paper, which consists of two elementary chemical reactions at the surface of the silicon dioxide thin film.

134 citations


Patent
05 Oct 1993
TL;DR: In this article, a method for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film is described, using a quartz crystal microbalance.
Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

124 citations


Patent
25 Jan 1993
TL;DR: Anisotropic etch as mentioned in this paper employs an anisotropic enchant for silicon such as KOH or ethylene diamine para-catechol, which is done from the backside 12b of the wafer to the front side 12a, and terminates on the dielectric layer on the frontside.
Abstract: An ink fill slot 18 can be precisely manufactured in a substrate 12 utilizing photolithographic techniques with chemical etching. N-type silicon wafers are double-side coated with a dielectric layer 26 comprising a silicon dioxide layer and/or a silicon nitride layer. A photoresist step, mask alignment, and plasma etch treatment precede an anisotropic etch process, which employs an anisotropic etchant for silicon such as KOH or ethylene diamine para-catechol. The anisotropic etch is done from the backside 12b of the wafer to the frontside 12a, and terminates on the dielectric layer on the frontside. The dielectric layer on the frontside creates a flat surface for further photoresist processing of thin film resistors 16.

Journal ArticleDOI
TL;DR: It appears that chemical etching can improve the retention of ceramic laminate veneers without significant loss of strength.
Abstract: This project studied the effect of altering surface topography by chemical etching on the strength of a feldspathic porcelain and castable glass ceramic. Fifty specimens of each ceramic material were subjected to five different etch times (in groups of 10). A silane coupling agent and composite resin cement were applied. Specimens were then subjected to a three-point flexural strength test. Representative specimens were examined under scanning electron microscope to elucidate more information on the effect and the depth of etch. There was no significant difference in the mean flexural strengths between the etched and nonetched groups and no significant difference between the different etching times for either material. Photomicrographs revealed dissimilar etch depths and selective dissolution of the phases. It appears that chemical etching can improve the retention of ceramic laminate veneers without significant loss of strength.

Patent
K. Yamagata1, T. Yonehara1
29 Jan 1993
TL;DR: In this paper, a process for producing a semiconductor substrate comprises the steps of forming a porous layer in a first substrate comprising monocrystalline silicon, forming a protective film on a side wall of the pores of the porous layer, and bonding the surface of the nonporous mon-polysilicon layer onto a second substrate with interposition of an insulating layer.
Abstract: A process for producing a semiconductor substrate comprises the steps of forming a porous layer in a first substrate comprising monocrystalline silicon; forming a protective film on a side wall of the pores of the porous layer; forming a nonporous monocrystalline silicon layer on the porous layer; bonding the surface of the nonporous monocrystalline silicon layer onto a second substrate with interposition of an insulating layer; and etching off selectively the porous layer by use of a chemical etching solution.

Patent
07 Dec 1993
TL;DR: In this article, the etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a Wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapour.
Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapour. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapour partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Journal ArticleDOI
TL;DR: In this article, an ex situ etching with various solutions of hydrofluoric acid (HF) and ammonium fluoride (NH4F) was performed on Si(111) samples and characterized by scanning tunneling microscopy (STM).
Abstract: After ex situ etching with various solutions of hydrofluoric acid (HF) and ammonium fluoride (NH4F) Si(111) samples are transferred into ultrahigh vacuum with an ultrafast load‐lock and characterized by scanning tunneling microscopy (STM): Concentrated HF selectively removes any surface oxide and, thus chemically prepares the initially burried, isotropically rough Si/SiO2 interface while highly buffered HF (i.e., NH4F) attacks bulk silicon anisotropically. After a rapid homogenization of the chemical surface termination (HF: various hydrides, fluorine, ...) towards a perfect, unreconstructed monohydride phase, Si(111)‐(1×1):H, NH4F etching leads to a time‐dependent transformation of isotropic roughness into a pattern of triangular etch defects with monohydride steps perpendicular to <211≳ due to a preferential removal of lower‐coordinated atomic defect sites. A predominant atomic step structure due to sample miscut (vicinal surfaces with azimuth ≠<211≳) can oppose the anisotropic NH4F etching: At low st...

Journal ArticleDOI
TL;DR: In this paper, a 50 nm thick double layer of low and high molecular weight polymethylmethacrylate resist was exposed with an 80 kV electron beam of diameter smaller than 5 nm and the resist was developed in 3:7 cellusolve: methanol with ultrasonic agitation during development.
Abstract: We report the fabrication of high aspect ratio, sub‐10 nm size, structures in silicon without involving any wet chemical etching. A 50 nm thick double layer of low and high molecular weight polymethylmethacrylate resist was exposed with an 80 kV electron beam of diameter smaller than 5 nm. After exposure the resist was developed in 3:7 cellusolve: methanol with ultrasonic agitation during development. A 5 nm thick AuPd film was deposited by ionized beam evaporation and a metal pattern was obtained by liftoff. Sub‐10 nm AuPd dots were recorded with a scanning electron microscope. The AuPd pattern was then used as a mask on the Si substrate which was etched with reactive ion etching. Silicon nanocolumns with diameters ranging from 5 to 7 nm and an aspect ratio of height to diameter of about 7:1 were obtained.

Patent
17 Nov 1993
TL;DR: In this paper, a process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches, was described.
Abstract: A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

Patent
26 Feb 1993
TL;DR: In this article, a method for forming high aspect ratio features such as trenches in a semiconductor structure includes dry etching a substrate in a glow discharge system at elevated temperature, which increases the etch rate for forming the features, and allows features with very high aspect ratios to be formed at a high etch speed.
Abstract: A method for forming high aspect ratio features such as trenches in a semiconductor structure includes dry etching a substrate in a glow discharge system at elevated temperature. With the dry etching carried out at an elevated temperature of between about 300° to 1100° C., the diffusion of a reactant gas into the features is increased and the diffusion of byproduct molecules out of the features is increased. This increases the etch rate for forming the features, and allows features with very high aspect ratio to be formed at a high etch rate.

Journal ArticleDOI
TL;DR: In this article, gas assisted etching with a finely focused ion beam has been studied, and the results show that a high scan speed, high gas flux, and low current density give the maximum enhancement in the etch rate over sputtering.
Abstract: Gas‐assisted etching with a finely focused ion beam has been studied. The presence of a reactive gas, in this case Cl2, results in an enhanced etch rate compared to the rate for sputtering for many materials, including Si, Al, and GaAs. Other advantages over sputtering are the absence of redeposited material and the high etch selectivity possible with some material combinations, which has been exploited in the etching of microstructures. In some applications of this technique, a protective layer of low etch rate material is used over the substrate to improve the quality of the etched structure. The characteristics of the etching process have been studied with variation in the scan speed, gas flux, and current density into the scanned area. In general, a high scan speed, high gas flux, and low current density were found to give the maximum enhancement in the etch rate over sputtering. The application of these results to etching over a wide range of experimental conditions is discussed, to give a basis for estimating the etching results that would occur under other conditions.

Patent
06 Aug 1993
TL;DR: In this article, a contact pad formed between a chip passivating layer (15) and a solder bump (10) is disclosed for producing a graded or stepped edge profile, which reduces edge stress that tends to cause cracking in the underlying passivation layer.
Abstract: Etching processes are disclosed for producing a graded or stepped edge profile in a contact pad formed between a chip passivating layer (15) and a solder bump (10). The stepped edge profile reduces edge stress that tends to cause cracking in the underlying passivating layer (15). The pad comprises a bottom layer (14) of chromium, a top layer (12) of copper and an intermediate layer (13) of phased chromium-copper. An intermetallic layer (13) of CuSn forms if and when the solder is reflowed, in accordance with certain disclosed variations of the process. In all the variations, the solder (10) is used as an etching mask in combination with several different etching techniques including electroetching, wet etching, anisotropic dry etching and ion beam etching.

Journal ArticleDOI
TL;DR: In this paper, the lamellar structures within spherulites of melt-crystallized poly(vinylidene fluoride) have been examined following the development of an etching technique which allows the study of representative morphologies in this polymer.
Abstract: The lamellar structures within spherulites of melt-crystallized poly(vinylidene fluoride) have been examined following the development of an etching technique which allows the study of representative morphologies in this polymer. The banded α-spherulites, which predominate at crystallization temperatures below ∼165°C, are found to be made up of densely packed lamellae with an intrinsically planar habit, whilst the γ-spherulites which develop preferentially at higher temperatures, have a curious architecture in which the lamellae adopt a highly curved “scroll-like” morphology. These observations are discussed in terms of existing models for spherulite banding and non-planar lamellar habits.

Journal ArticleDOI
U. Neuwald1, H.E. Hessel1, A. Feltz1, Ulrich Memmert1, Rolf Jürgen Behm1 
TL;DR: In this article, the authors investigated the etching of hydrogen terminated Si(100) wafer surfaces in 40% aqueous NH4F solution by scanning tunneling microscopy.

Patent
James F. O'Neill1
01 Nov 1993
TL;DR: In this paper, a two-step anisotropic etching process from a single side of the wafer is described using an ink flow directing part of a thermal ink jet printhead where the coarse etching step provides the reservoir and the timed fine etching stage provides the ink channels having varying cross-sectional flow areas.
Abstract: Three dimensional silicon structures having variable depths such as ink flow channels and reservoirs are fabricated from silicon wafers by a two-step anisotropic etching process from a single side of the wafer. Two different etching masks are formed one on top of the other prior to the initiation of etching with the coarsest mask formed last and used first. Once the coarse anisotropic etching is completed, the coarse etch mask is removed and the finer anisotropic etching is accomplished through the remaining mask. The shape of the mask for the finer anisotropic etching in combination with a predetermined etch time produces a channel having varying depths and widths by controlled undercutting of the mask by the finer anisotropic etching. The preferred embodiment is described using an ink flow directing part of a thermal ink jet printhead where the coarse etching step provides the reservoir and the timed fine etching step provides the ink channels having varying cross-sectional flow areas.

Patent
29 Mar 1993
TL;DR: In this article, a tungsten etchant was used to remove the material from the alignment marks through wet etching without the need for any photo steps, and the alignment constraints vis-a-vis the etchant dispensing apparatus and wafer are not very critical and the live dice are easily protected from the wet etch.
Abstract: The present invention remedies the problems associated with selective etching of material, and in particular tungsten, by locally removing the material (e.g. tungsten) from the alignment marks through wet etching without the need for any photo steps. Either before or after chemical mechanical polishing, the wafers are flatly aligned and a tungsten etching agent is introduced through an etchant dispensing apparatus onto the alignment marks. Since an alignment mark is normally a few hundred microns in size and there is a large unused silicon real estate around the alignment marks, the alignment constraints vis-a-vis etchant dispensing apparatus and wafer are not very critical and tungsten plugs in the live dice are easily protected from the wet etch. After the etch, the etching byproduct is removed by suction and the wafer is cleaned by being rinsed in distilled water.

Journal ArticleDOI
TL;DR: In this paper, an extension of atomic layer epitaxy (ALE) to a porous, high-surface-area substrate commonly used in catalysis is presented, where various analytical and chemical techniques, in addition to the high vacuum techniques, can be applied in the study of surface reaction sand surface species in ALE after a single reaction step.

Journal ArticleDOI
TL;DR: In this article, the first spectroscopic ellipsometry study of the E0, E0+Δ 0, E1, and E1+ Δ 1 critical points in high-quality ZnSe films was reported.
Abstract: We report the first spectroscopic ellipsometry study of the E0, E0+Δ0, E1, and E1+Δ1 critical points in high‐quality ZnSe films. These data seem to be the best identification of E1 and E1+Δ1 peaks to date using ellipsometry. We also describe a chemical etching procedure which was successfully used to remove the natural surface oxide overlayer on the ZnSe films. X‐ray photoelectron spectroscopy data after NH4OH treatment shows the disappearance of oxygen and oxidized Se peaks demonstrating the successful removal of surface oxide overlayer on ZnSe.

Patent
22 Dec 1993
TL;DR: In this article, a process for etching aluminum from a substrate, where portions of the aluminum are protected by a resist material, is described, and a process gas comprising HCl, Cl-containing etchant and N₂ is introduced in the chamber.
Abstract: A process for etching aluminum from a substrate, where portions of the aluminum are protected by a resist material, is described. The substrate is placed into a chamber and a process gas comprising HCl, Cl-containing etchant and N₂ is introduced in the chamber. A plasma is generated in the chamber to generate from the process gas an etch gas that etches aluminum from the substrate at fast rates, with good selectivity, reduced profile microloading, and substantially only anisotropic etching.

Journal ArticleDOI
TL;DR: In this paper, side-wall profiles in etched grooves were used to produce two-dimensional etch diagrams for micromachining of monocrystalline quartz in, for instance, hydrofluoride-based etchants.
Abstract: The etch rate in monocrystalline quartz depends on the crystalline orientation. Etch-rate diagrams for micromachining of monocrystalline quartz in, for instance, hydrofluoride-based etchants, are a necessity if one requires the best manufacturing conditions for an etched structure. In this paper we use the development of side-wall profiles in etched grooves, on a Z-cut quartz wafer, to produce two-dimensional etch diagrams. The etch conditions are eight combinations of temperature, from 22 degrees C to 80 degrees C, and etchant mixtures of HF and NH4F diluted in water.

Patent
14 Jan 1993
TL;DR: In this article, an ozone/oxygen mixture (O3 /O2) having optimally high ozone concentration is added to the reaction chamber to clean parasitic layers of silicon oxides or nitrides in a reaction chamber, in which at least one fluoridated carbon, particularly CF4 and/or C2 F6, is the main constituent.
Abstract: For cleaning parasitic layers of silicon oxides or nitrides in a reaction chamber, an etching gas mixture is employed in which at least one fluoridated carbon, particularly CF4 and/or C2 F6, is the main constituent. Then, an ozone/oxygen mixture (O3 /O2) having optimally high ozone concentration is added to the reaction chamber. The etching gas mixture is excited in the reaction chamber by triggering the etching gas mixture to form a plasma, having extremely low power with an excitation frequency in the RF range. The etching gas mixture etches all surfaces in the reaction chambers free of residues with a high etching rate.

Patent
Tsuneshi Nakamura1
28 Sep 1993
TL;DR: In this article, the adhesion between the insulating resin layer and a plating layer (i.e., a circuit conductive layer) is improved by a dry sandblasting treatment.
Abstract: A dry sandblasting treatment for spraying abrasives onto a surface of an insulating resin layer, a chemical etching for chemically etching the surface, and a plating process for plating a conductive layer on the resulting insulating resin layer are successively performed. Since the surface of the insulating resin layer is roughened by the dry sandblasting treatment and the resulting surface is subjected to the chemical etching, a minute anchor structure is formed on the surface. Accordingly, the adhesion between the insulating resin layer and a plating layer (i.e., a circuit conductive layer) is improved. Due to the dry sandblasting treatment, the shape of a via hole formed in the insulating resin layer is improved, and an exposed surface of the circuit conductor layer and an inner wall of a through-hole are cleaned.