Showing papers on "Memistor published in 2012"

A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications

Abstract: Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

Memristor Emulator for Memristor Circuit Applications

Abstract: A memristor emulator which imitates the behavior of a TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO2 memristor model in real circuit.

Neural Synaptic Weighting With a Pulse-Based Memristor Circuit

Abstract: A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.

Memristor Bridge Synapses

Abstract: In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Abstract: Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

A Novel Design and Modeling Paradigm for Memristor-Based Crossbar Circuits

Abstract: Over 30 years ago L. Chua proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices. The unique electrical characteristics associated with them, along with the advantages of crossbar structures, have the potential to revolutionize computing architectures. A well-defined and effective memristor model for circuit design combined with a design paradigm based on well-understood underlying logic design principles would certainly accelerate research on nanoscale circuits and systems. Toward this goal, we propose a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling. We use this circuit model to design and simulate various logic circuit designs capable of universal computation. Finally, we develop and present a new design paradigm for memristor-based crossbar circuits.

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

Abstract: Design of hybrid circuits and systems based on CMOS and nano-device requires rethinking of fundamental circuit analysis to aid design exploration. Conventional circuit analysis with modified nodal analysis (MNA) cannot consider new nano-devices such as memristor together with the traditional CMOS devices. This paper has introduced a new MNA method with magnetic flux (Φ) as new state variable. New SPICE-like circuit simulator is thereby developed for the design of hybrid CMOS and memristor circuits. A number of CMOS and memristor-based designs are explored, such as oscillator, chaotic circuit, programmable logic, analog-learning circuit, and crossbar memory, where their functionality, performance, reliability and power can be efficiently verified by the newly developed simulator. Specifically, one new 3-D-crossbar architecture with diode-added memristor is also proposed to improve integration density and to avoid sneak path during read-write operation.

A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators

Abstract: A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

Abstract: With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory

Memristor crossbar based hardware realization of BSB recall function

Abstract: The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resource requirement, we propose a hardware realization by utilizing memristor crossbar arrays. Memristors can remember the historical profiles of the excitations and record them as analog variables. The similarity to biological synaptic behavior has encouraged a lot of research on memristor-based neuromorphic hardware system. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specifically, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constraints when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduce directional noise and hence dominate the quality of the circuit.

Low power memristor-based ReRAM design with Error Correcting Code

Abstract: The emerging memristor-based Resistive RAM (ReRAM) has shown great potential as one of the most promising memory technologies, with the unique properties such as high density, low-power, good-scalability, and non-volatility However, as the process technology scales, the process variation will cause the deviation of the actual electrical behavior of memristor Recently, researchers have observed that the probability of a single ReRAM cell switching successfully follows a function of the logarithm of the total programming time As a result, the uncertainty of the electrical behavior results in different degrees of error rates in ReRAM-based memory Traditional ECC (Error Correcting Code) design for conventional DRAM memory is used to detect and correct the errors in the memory system In this paper, based on the mathematical analysis of the error patterns in memristor-based ReRAM and the study of ECC designs, we proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both the MOS based and cross-point based memristor ReRAM designs In addition, the performance/power/area overhead of the proposed design options is also evaluated in detail

Models of memristors for SPICE simulations

Abstract: Memristors are novel devices which can be used in applications such as memory, logic, analog circuits, and neuromorphic systems. Several memristor technologies have been developed such as ReRAM (Resistive RAM), MRAM (Magnetoresistance RAM), and PCM (Phase Change Memory). To design circuits with memristors, the behavior of the memristor needs to be described by a mathematical model. While the model for memristors should be sufficiently accurate as compared to the behavior of physical devices, the model must also be computationally efficient. Several models for memristors have been proposed — the linear ion drift model, the nonlinear ion drift model, the Simmons tunnel barrier model, and the ThrEshold Adaptive Memristor (TEAM) model. In this paper, the different memristor models are described and a Verilog-A implementation for these models, including the relevant window functions, are presented. These models are suitable for EDA tools such as SPICE.

Implementation of an analogue model of a memristor based on a light-dependent resistor

Abstract: In this paper, an analogue model of a memristor using a light-dependent resistor (LDR) is presented. This model can be simplified into two parts: a control circuit and a variable resistor. It can be used to easily verify theoretical presumptions about the switching properties of memristors. This LDR-based memristor model can also be used in both simulations and experiments for future research into memristor applications. The paper includes mathematical models, simulations, and experimental results.

Memristor-based RRAM with applications

Abstract: Recently acclaimed the fourth fundamental circuit element, the memristor was theoretically predicted by Leon Chua in 1971, although its single device electronic implementation eluded the attention of integrated circuit designers for the past three decades and was first reported in 2008 by the Hewlett-Packard (HP) Laboratory researchers while developing crossbar-based ultra high-density nonvolatile memories. Memristor-based hybrid nanoscale CMOS technology is expected not only to impact the flash memory industries profoundly, but also to revolutionize digital and neuromorphic computing. The memristor exhibits a dynamical resistance state that depends on its excitation history and which can be exploited to build transistor-less nonvolatile semiconductor memory (NVSM), commonly known as resistive RAM (RRAM). This paper addresses an implementation scheme for memristor-based resistive random access memory (MRRAM), a nano-scale binary memory that is compatible with modern computer systems. Its structure is similar to that of static random access memory (SRAM), but with the memristor replacing the underlying RS flip-flop. By improving the MRRAM, we propose a multilevel memory with greater data density, which stores multiple bit information in gray-scale form in a memory unit. Reported computer simulations and numerical analyses verify the effectiveness of the proposed scheme in storing ASCII characters and gray-scale images in binary format.

Delayed switching applied to memristor neural networks

Abstract: Magnetic flux and electric charge are linked in a memristor. We reported recently that a memristor has a peculiar effect in which the switching takes place with a time delay because a memristor possesses a certain inertia. This effect was named the “delayed switching effect.” In this work, we elaborate on the importance of delayed switching in a brain-like computer using memristor neural networks. The effect is used to control the switching of a memristor synapse between two neurons that fire together (the Hebbian rule). A theoretical formula is found, and the design is verified by a simulation. We have also built an experimental setup consisting of electronic memristive synapses and electronic neurons.

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device

Abstract: The use of low voltage circuits and power-off mode help to reduce the power consumption of chips. Non-volatile logic (nvLogic) and nonvolatile SRAM (nvSRAM) enable a chip to preserve its key local states and data, while providing faster power-on/off speeds than those available with conventional two-macro schemes. Resistive memory (memristor) devices feature fast write speed and low write power. Applying memristors to nvLogic and nvSRAMs not only enables chips to achieve low power consumption for store operations, but also achieve fast power-on/off processes and reliable operation even in the event of sudden power failure. However, current memristor devices suffer from limited endurance, which influences the design of the circuit structure for memristor-based nvLogic and nvSRAM. Moreover, previous nvLogic/nvSRAM circuits cannot achieve low voltage operation. This paper explores various circuit structures for nvLogic and nvSRAM, taking into account memristor endurance, especially for low-voltage applications.

Memristor-based synapse design and training scheme for neuromorphic computing architecture

Abstract: Memristors have been rediscovered recently and then gained increasing attentions. Their unique properties, such as high density, nonvolatility, and recording historic behavior of current (or voltage) profile, have inspired the creation of memristor-based neuromorphic computing architecture. Rather than the existing crossbar-based neuron network designs, we focus on memristor-based synapse and the corresponding training circuit to mimic the real biological system. In this paper, first, the basic synapse design is presented. On top of it, we will discuss the training sharing scheme and explore design implication on multi-synapse neuron system. Energy saving method such as self-training is also investigated.

Memristive XOR for resistive multiplier

Abstract: A new memristors-based resistive logic computation unit is introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's status.

Realization of an analog model of memristor based on light dependent resistor

Abstract: In this paper, a memristor analog model based on a light dependent resistor (LDR) is presented. This model can be simplified into two parts: a control circuit and a variable resistor. It can be used to easily verify theoretical presumptions about the properties of memristors. This LDR based memristor model can also be used in both simulations and experiments for future research into memristor applications. Mathematical models that describe the behaviors are derived. Multisim simulations and experimental results are given as well.

Implementing logic circuits with memristors

Abstract: Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

Statistical memristor modeling and case study in neuromorphic computing

Abstract: Memristor, the fourth passive circuit element, has attracted increased attention since it was rediscovered by HP Lab in 2008. Its distinctive characteristic to record the historic profile of the voltage/current creates a great potential for future neuromorphic computing system design. However, at the nano-scale, process variation control in the manufacturing of memristor devices is very difficult. The impact of process variations on a memristive system that relies on the continuous (analog) states of the memristors could be significant. We use TiO 2 -based memristor as an example to analyze the impact of geometry variations on the electrical properties. A simple algorithm was proposed to generate a large volume of geometry variation-aware three-dimensional device structures for Monte-Carlo simulations. A neuromorphic computing system based on memristor-based bidirectional synapse design is proposed as case study. We analyze and evaluate the robustness of the proposed system in pattern recognition based on massive Monte-Carlo simulations, after considering input defects and process variations.

Mathematical modeling of a memristor device

Abstract: The realization of the missing fourth element by Hewlett-Packard in 2008, the memristor, adds new promising technology that enables the continuing improvement of performance, power and cost of integrated circuits and keeping Moore's law alive. Memristor-based technology provides much better scalability, higher utilization when used as memory, and overall lower power consumption. This paper presents a detailed study of existing memristor modeling using Matlab simulations. We studied three different models to predict the behavior of the memristor device. We developed the Matlab algorithms for all models and analyzed them for their compatibility with the experimentally established characteristics of HP memristor, as well as their viability for use in memory circuits. We discussed all the difficulties with these models and adopt a modified model that gives more realistic description of a memristor device.

Development Of Memristor Based Circuits

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Memistor Is Not Memristor [Express Letters]

Abstract: This note clarifies the circuit-theoretic differences between a memristor and a memistor.

The influences of model parameters on the characteristics of memristors

Abstract: As the fourth passive circuit component, a memristor is a nonlinear resistor that can "remember" the amount of charge passing through it. The characteristic of "remembering" the charge and non-volatility makes memristors great potential candidates in many fields. Nowadays, only a few groups have the ability to fabricate memristors, and most researchers study them by theoretic analysis and simulation. In this paper, we first analyse the theoretical base and characteristics of memristors, then use a simulation program with integrated circuit emphasis as our tool to simulate the theoretical model of memristors and change the parameters in the model to see the influence of each parameter on the characteristics. Our work supplies researchers engaged in memristor-based circuits with advice on how to choose the proper parameters.

A new CMOS based memristor implementation

Abstract: In 1971, memristor theory was proposed and described by Leon Chua. But first practical implementation has been realized by a group of researchers from Hewlett-Packard laboratories in 2008. Memristor has drawn the worldwide attention after this innovation. This work introduces a new CMOS based memristor realization employing DDCC (Differential Difference Current Conveyor) based circuit blocks which are easy for VLSI implementation. Simulation results show that the realization proposed satisfies memristor properties and it can be well applied to chaotic secure communication circuits.

SPICE simulator for hybrid CMOS memristor circuit and system

Abstract: Memristor is a two-terminal non-linear passive electrical device. After its recently successful fabrication, a variety of applications based on memristor have been explored, such as non-volatile memory, reconfigurable computing and neural network. However, one major challenge when designing hybrid CMOS memristor integrated circuit is the lack of SPICE-like simulator for design validation. Current approach is to describe memristor device with equivalent circuit, which is however extremely time-consuming for large scale design simulation due to additional modeling components. In this paper, a memristor SPICE simulator is introduced based on the recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variable such as doping ratio of memristor. As such, the memristor device can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32×32 memristor crossbar circuit. A hybrid CMOS memristor circuit for classic conditioning training has also been studied by the developed SPICE simulator.

Memristor circuit for artificial synaptic weighting of pulse inputs

Abstract: This paper presents a memristor based new synaptic circuit, consisting of five memristor in a bridge structure together with one differential amplifier. The circuit is able to perform positive and negative weighting for pulse type inputs in neural cells. Processing is conducted with applied pulses at a common terminal in different time slots. It is compact, non-volatile and low power efficient. Simulations of sign setting, weight setting and synaptic multiplication are performed with hp TiO 2 memristor models.

Emergence of competitive control in a memristor-based neuromorphic circuit

Abstract: Recent work in neuroscience is revealing how the blowfly rapidly detects orientation using neural circuits distributed directly behind its photo receptors. These circuits like all biological systems rely on timing, competition, feedback, and energy optimization. The recent realization of the passive memristor device, the so-called fourth fundamental passive element of circuit theory, assists with making low power biologically inspired parallel analog computation achievable. Building on these developments, we present a memristor-based neuromorphic competitive control (mNCC) circuit, which utilizes a single sensor and can control the output of N actuators delivering optimal scalable performance, and immunity from device variation and environmental noise.

Why Are Memristor and Memistor Different Devices

Abstract: This paper presents a circuit-theoretic foundation of the “memristor,” and clarifies why it is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memistor.” Here we show that while the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory, the memistor is an ad hoc 3-terminal gadget devised for one specific application, and does not qualify as a 3-terminal circuit element because it is impossible to predict its behavior when connected with other circuit elements.