Showing papers on "p–n junction published in 1996"

Semiconductor device fundamentals

Abstract: I. SEMICONDUCTOR FUNDAMENTALS. 1. Semiconductors -- A General Introduction. General Material Properties. Crystal Structure. Crystal Growth. 2. Carrier Modeling. The Quantization Concept. Semiconductor Models. Carrier Properties. State and Carrier Distributions. Equilibrium Carrier Concentrations. 3. Carrier Action. Drift. Diffusion. Recombination -- Generation. Equations of State. Supplemental Concepts. 4. Basics of Device Fabrication. Fabrication Processes. Device Fabrication Examples. R1. Part I Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part I Review Problem Sets and Answers. IIA. PN JUNCTION DIODES. 5. PN Junction Electrostatics. Preliminaries. Quantitative Electrostatic Relationships. 6. PN Junction Diode -- I-V Characteristics. The Ideal Diode Equation. Deviations from the Ideal. Special Considerations. 7. PN Junction Diode -- Small-Signal Admittance. Introduction. Reverse-Bias Junction Capacitance. Forward-Bias Diffusion Admittance. 8. PN Junction Diode -- Transient Response. Turn-Off Transient. Turn-On Transient. 9. Optoelectronic Diodes. Introduction. Photodiodes. Solar Cells. LEDs. IIB. BJTS AND OTHER JUNCTION DEVICES. 10. BJT Fundamentals. Terminology. Fabrication. Electrostatics. Introductory Operational Considerations. Performance Parameters. 11. BJT Static Characteristics. Ideal Transistor Analysis. Deviations from the Ideal. Modern BJT Structures. 12. BJT Dynamic Response Modeling. Equivalent Circuits. Transient (Switching) Response. 13. PNPN Devices. Silicon Controlled Rectifier (SCR). SCR Operational Theory. Practical Turn-on/Turn-off Considerations. Other PNPN Devices. 14. MS Contacts and Schottky Diodes. Ideal MS Contacts. Schottky Diode. Practical Contact Considerations. R2. Part II Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part II Review Problem Sets and Answers. III. FIELD EFFECT DEVICES. 15. Field Effect Introduction -- the J-FET and MESFET. General Introduction. J-FET. MESFET. 16. MOS Fundamentals. Ideal Structure Definition. Electrostatics -- Mostly Qualitative. Electrostatics -- Quantitative Formulation. Capacitance-Voltage Characteristics. 17. MOSFETs -- The Essentials. Qualitative Theory of Operation. Quantitative ID - VD Relationships. ac Response. 18. Nonideal MOS. Metal-Semiconductor Workfunction Difference. Oxide Charges. MOSFET Threshold Considerations. 19. Modern FET Structures. Small Dimension Effects. Select Structure Survey. R3. Part III Supplement and Review. Alternative/Supplemental Reading List. Figure Sources/Cited References. Review List of Terms. Part III Review Problem Sets and Answers. Appendix A. Elements of Quantum Mechanics. Appendix B. MOS Semiconductor Electrostatics -- Exact Solution. Appendix C. MOS C-V Supplement. Appendix D. MOS I-Vsupplement. Appendix E. List of Symbols. Appendix M. MATLAB Program Script.

Polymer Light-Emitting Electrochemical Cells: In Situ Formation of a Light-Emitting p-n Junction.

Abstract: Solid-state polymer light-emitting electrochemical cells have been fabricated using thin films of blends of poly(1,4-phenylenevinylene) and poly(ethylene oxide) complexed with lithium trifluoromethanesulfonate. The cells contain three layers: the polymer film (as the emissive layer) and indium-tin oxide and aluminum films as the two contact electrodes. When externally biased, the conjugated polymers are p-doped and n-doped on opposite sides of the polymer layer, and a light-emitting p-n junction is formed in between. The admixed polymer electrolyte provides the counterions and the ionic conductivity necessary for doping. The p-n junction is dynamic and reversible, with an internal built-in potential close to the band gap of the redox-active conjugated polymer (2.4 eV for PPV). Green light emitted from the p-n junction was observed with a turn-on voltage of about 2.4 V. The devices reached 8 cd/m(2) at 3 V and 100 cd/m(2) at 4 V, with an external quantum efficiency of 0.3-0.4% photons/electron. The response speed of these cells was around 1 s, depending on the diffusion of ions. Once the light-emitting junction had been formed, the subsequent operation had fast response (microsecond scale or faster) and was no longer diffusion-controlled.

Development of transient current and charge techniques for the measurement of effective net concentration of ionized charges (Neff) in the space charge region of p-n junction detectors☆

Abstract: Transient current and charge techniques (TCT/TChT) have been developed as alternatives to the standard C-V measurements for measurements of the effective net concentration of ionized charges (Neff) in the space charge region (SCR) of Si p-n junction detectors, especially for heavily irradiated detectors. This paper contains the physical background of the techniques, modeling of current and charge pulse response, and applications of the methods to the characterizations of silicon planar detectors designed for high energy physics.

Semiconductor laser having a structure of photonic bandgap material

Abstract: Disclosed is a semiconductor laser that is constituted by at least one active layer sandwiched between two confinement layers with P and N type doping to constitute a PN junction. In at least one of the confinement layers and/or the active layer, holes are designed on each side of the cavity so as to form structures of photonic bandgap material along the lateral walls of the cavity and the ends of the cavity.

SiC semiconductor device comprising a pn junction with a voltage absorbing edge

Abstract: A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

Carrier transport in porous silicon light-emitting devices

Abstract: This work presents a comprehensive investigation of carrier transport properties in light‐emitting porous silicon (LEPSi) devices. Models that explain the electrical characteristics and the electroluminescence properties of the LEPSi devices are developed. In metal/LEPSi devices, the forward current density–voltage (J–V) behavior follows a power law relationship (J∼Vm), which indicates a space charge current attributed to the carriers drifting through the high resistivity LEPSi layer. In LEPSi pn junction devices, the forward J–V behavior follows an exponential relationship (J∼eeV/nkT), which indicates that the diffusion of carriers makes a major contribution to the total current. The temperature dependence of the J–V characteristics, the frequency dependence of the capacitance–voltage characteristics, and the frequency dependence of the electroluminescence intensity support the models. Analysis of devices fabricated with a LEPSi layer of 80% porosity results in a relative permittivity of ∼3.3, a carrier ...

18.2% (AM1.5) efficient GaAs solar cell on optical-grade polycrystalline Ge substrate

Abstract: In this work, the authors present GaAs material and device-structure optimization studies that have led to achieve a open-circuit voltage of /spl sim/1 volt and a best solar cell efficiency of 18.2% under AM1.5G illumination, for a 4 cm/sup 2/ area GaAs cell on commercially-available, cast, optical-grade polycrystalline Ge substrate. This V/sub /spl infin// is almost 70 mV higher than on their previously-reported best GaAs cell on similar substrates. They discuss the growth of high-quality GaAs-AlGaAs layers, across the various crystalline orientations of a polycrystalline Ge substrate, important for obtaining good device performance. Optimization studies of the minority-carrier properties of GaAs layers on poly-Ge substrates have revealed that lifetime-spread across various grains can be reduced through the use of lower doping for the Al/sub 0.8/Ga/sub 0.2/As confinement layers. The cell-structure optimization procedures for improved V/sub /spl infin// and cell efficiency, include the use of thinner emitters, a spacer layer near the p/sup +/-n junction and an improved window layer. An experimental study of dark currents in these junctions, with and without the spacer, as a function of temperature (77 K to 288 K) is presented indicating that the spacer reduces the tunneling contribution to dark current.

Colour detection using a buried double p-n junction structure implemented in the CMOS process

Abstract: The authors present a novel technique for monochromatic colour detection. By using a buried double p-n junction (BDJ) structure, wavelength-dependent photocurrents I1 and I2 can be measured. And the incident light wavelength can be identified from the ratio I2/I1. The device operation was verified with a test circuit implemented in CMOS process.

Low energy response of silicon pn-junction detector

Abstract: The response function of implanted silicon detectors in the soft X-ray region (150 eV-6 keV) has been measured. To reduce signal charge loss in the highly doped p + -region just beneath the detector surface, different techniques of producing shallow doping profiles and enhancing the electric field at the pn-junction are presented. The spectroscopic resolution could be improved significantly. On 〈100〉 detector material, a peak to valley ratio of 5700: 1 for the mangan K α line was achieved. The measured pulse-height distributions were fitted by a detector model, taking the doping profile of the entrance window into account. The results of the fit were in excellent agreement with the measurement data over the entire energy range.

Type conversion of p-(HgCd)Te using and Ar reactive ion etching

Abstract: Hydrogen/methane gas mixtures and pure argon were used for reactive ion etching (RIE) of ( and 0.28). The effect of the ratio on the depth of the etched surface and the depth of the p - n junction created under the etched surface were studied for the RIE process. It was found that the etch depth reaches a maximum at an ratio and the depth of the p - n junction decreases with increasing fraction in the mixture. The roughness of the etched surface is smallest using a gas mixture with a small amount of (20 - 30%). For the pure Ar RIE process the etch and p - n junction depths were studied as functions of etch time, Ar pressure and rf power. Clear evidence for the creation of p - n junctions using various kinds of Ar RIE processes is found.

Organic vapor sensitivity in a porous silicon device

Abstract: An organic vapor sensitive device using anodized porous silicon has been developed The device consists of two pn junctions surrounded by the porous silicon layer as a vapor sensing element The devices show an increase of current for exposure to thousands ppm of organic vapor at room temperature A high sensitivity is observed for ethanol vapor The porous silicon combined with the reverse biased pn junction plays an important role for vapor sensing It is discussed that the adsorption of polar molecules in the vicinity of pn junction induces a ‘soft’ breakdown in the reverse biased pn junction

Diffusion mask and fabrication method for forming pn-junction elements in a compound semiconductor substrate

Abstract: A pn-junction element is formed in a compound semiconductor substrate by depositing an aluminum-nitride film on the surface of the substrate, patterning the aluminum-nitride film to form a diffusion mask, depositing a diffusion source film on the diffusion mask, diffusing an impurity from the diffusion source film into the substrate, and removing the diffusion source film with buffered hydrofluoric acid. Electrode lines can then be formed directly on the aluminum-nitride diffusion mask, which is not etched by buffered hydrofluoric acid.

Improved modeling of grain boundary recombination in bulk and p‐n junction regions of polycrystalline silicon solar cells

Abstract: This article provides a theoretical investigation of recombination at grain boundaries in both bulk and p‐n junction regions of silicon solar cells. Previous models of grain boundaries and grain boundary properties are reviewed. A two dimensional numerical model of grain boundary recombination is presented. This numerical model is compared to existing analytical models of grain boundary recombination within both bulk and p‐n junction regions of silicon solar cells. This analysis shows that, under some conditions, existing models poorly predict the recombination current at grain boundaries. Within bulk regions of a device, the effective surface recombination velocity at grain boundaries is overestimated in cases where the region around the grain boundary is not fully depleted of majority carriers. For vertical grain boundaries (columnar grains), existing models are shown to underestimate the recombination current within p‐n junction depletion regions. This current has an ideality factor of about 1.8. An improved analytical model for grain boundary recombination within the p‐n junction depletion region is presented. This model considers the effect of the grain boundary charge on the electric field within the p‐n junction depletion region. The grain boundary charge reduces the p‐n junction electric field, at the grain boundary, enhancing recombination in this region. This model is in agreement with the numerical results over a wide range of grain boundary recombination rates. In extreme cases, however, the region of enhanced, high ideality factor recombination can extend well outside the p‐n junction depletion region. This leads to a breakdown of analytical models for both bulk and p‐n junction recombination, necessitating the use of the numerical model.

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

Abstract: Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10/sup 11/ atoms/cm/sup 2/ by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550/spl deg/C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved.

PN junction floating gate EEPROM, flash EPROM device

Abstract: Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl 3 doping are required to fabricate this device. The threshold voltage of this device well controlled by the ratio of C fp , capacitance of the P type capacitor and C fp capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

High-field fast-risetime pulse failures in 4H- and 6H-SiC pn junction diodes

Abstract: We report the observation of anomalous reverse breakdown behavior in moderately doped (2–3×1017 cm−3) small‐area micropipe‐free 4H‐ and 6H‐SiC pn junction diodes. When measured with a curve tracer, the diodes consistently exhibited very low reverse leakage currents and sharp repeatable breakdown knees in the range of 140–150 V. However, when subjected to single‐shot reverse bias pulses (200 ns pulsewidth, 1 ns risetime), the diodes failed catastrophically at pulse voltages of less than 100 V. We propose a possible mechanism for this anomalous reduction in pulsed breakdown voltage relative to dc breakdown voltage. This instability must be removed so that SiC high‐field devices can operate with the same high reliability as silicon power devices.

Bidirectional lateral insulated gate bipolar transistor

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Semiconductor light-emitting element

Abstract: PROBLEM TO BE SOLVED: To increase light output by forming at least a part of a side surface of a first semiconductor region to spread tiltingly toward the one main surface from a PN junction and that of a second semiconductor region to spread tiltingly toward the other main surface. SOLUTION: An upper part of a side surface of an N-type semiconductor region 12 below an exposure position of a P-N junction 18 is a tilting surface 19, formed so as to spread toward a lower surface 16 from the P-N junction 18. A side surface of a P-type semiconductor region 11 above an exposure position of the P-N junction 18 consists of a pair of tilting surfaces 20a, 20b and a pair of vertical surfaces 21a, 21b, and the tilting surfaces 20a, 20b are formed to spread toward an upper surface 14 from the P-N junction 18. A tilting surface of the first semiconductor 12 spreading to the one main surface direction effectively functions to totally reflect the light emitted from a P-N junction to have a transverse component at a small angle to the one main surface direction and increases a light pick up amount from the one main surface, thus increasing the light output.

Photoelectric cell having first and second insulated gates on first and second channel forming regions

Abstract: A photoelectric cell of the present invention comprises a first conduction type first semiconductor region; a second conduction type second semiconductor region formed in the surface of the first semiconductor region so as to form a pn junction together with the first semiconductor region; a first conductive region formed in the surface of the first semiconductor region so as to be separated from the second semiconductor region and to form a first rectifier junction together with the first semiconductor region; a second conductive region formed in the surface of the first semiconductor region so as to be separated from the first conductive region and to be electrically connected to the second semiconductor region to form a second rectifier junction together with the first semiconductor region; a third conductive region formed in the surface of the second semiconductor region so as to form a third rectifier junction together with the second semiconductor region; a first insulated gate formed on a first channel forming region in the surface of the first semiconductor region defined between the first conductive region and the second conductive region on and a second insulated gate formed on a second channel forming region in the surface of the second semiconductor region defined between the first semiconductor region and the third conductive region.

Improved Characteristics of p+-n Junctions formed by Excimer Laser Annealing with Low Temperature Pre-Annealing

Abstract: P+-n diodes with shallow junctions less than 50 nm deep were formed utilizing single pulse excimer laser annealing. The diode characteristics and the crystallinity near the junctions was investigated and it was found that the characteristics were improved by annealing the sample at 600° C for 1 h prior to excimer laser annealing. A low leakage current density of ≤10 nA/cm2 under reverse bias and ideal I–V curves of 60 mV/dec. over 7 decades under forward bias were obtained. The average leakage current and the device to device leakage current fluctuation were both reduced when the pre-annealing was used. The crystallinity near the junction was investigated by cross sectional transmission electron microscopy (TEM).

Semiconductor device comprising polysilicon interconnection layers separated by insulation films

Abstract: In a micro-patterned semiconductor device that uses thin-film polycrystalline silicon for both interconnection and TFT (Thin Film Transistor) configuration elements, the required current supply capacity is achieved by increasing the leakage current of a reverse-direction diode when the reverse-direction junction diode is present in the current path consisting of polycrystalline silicon. Leakage current is increased by steepening the density slope at the PN junction of the diode which consists of polycrystalline silicon, or by making the region near the junction amorphous. For example, sufficient current can be supplied to a large number of memory cells via reverse-direction diodes even when cells that use TFTs consisting of thin-film polycrystalline silicon as the load for the flip-flop are used as large-scale SRAM memory cells. In this way, ultra high-integration memory ICs can be realized.

DEPLETION REGION STOPPER FOR pn JUNCTION IN SILICON CARBIDE

Abstract: A semiconductor component and a method for processing said component, which comprises a pn junction, where both the p-conducting (3) and the n-conducting layers (2) of the pn junction constitute doped silicon carbide layers, where the junction is at the edge of the lower doped conducting layer terminated by a depletion region stopper (DRS) which exhibits a charge profile with a stepwise or uniformly increasing total charge and/or effective sheet charge density from a first lowest value to a highest value at the outermost edge (5) of the junction following a radial direction from the main junction towards the outermost edge.

Direct calculation of two‐dimensional collection probability in pn junction solar cells, and study of grain‐boundary recombination in polycrystalline silicon cells

Abstract: A new method for the direct calculation of the two‐dimensional collection probability in pn junction solar cells is presented. Based on its reciprocity properties, the inhomogeneous continuity equation for excess carriers is transformed to a homogeneous partial differential equation (PDE) for the probability of carriers being collected in the external circuit. The new PDE is easier to solve and directly gives the short‐circuit current. The method is applied to study the impact of grain‐boundary recombination on the performance of polycrystalline silicon solar cells. A critical grain width of four times the carrier diffusion length in the base is found to be the limiting boundary between polycrystalline behavior and monocrystalline behavior of the cell. The sensitivity of short‐circuit AM1.5 collection efficiency to the grain width Wg, the grain‐boundary recombination velocity Sg, minority‐carrier diffusion lengths, and surface recombination velocities, is quantified for a variety of cell types and recombination parameters. The sensitivity analysis indicates that AM1.5 collection efficiency is most sensitive to grain width in narrow grain cells, and to base diffusion length in wide grain cells.

Negative Conductance Properties in Extremely Thin Silicon-on-Insulator (SOI) Insulated-Gate pn-Junction Devices (SOI Surface Tunnel Transistors)

Abstract: In this paper the occurrence of negative conductance at temperatures of less than 90 K in a silicon-on-insulator (SOI) surface tunnel transistor with a 10-nm-thick silicon layer fabricated on a separation by implanted oxygen (SIMOX) substrate is reported. Through comparison with the performance of an SOI surface tunnel transistor with a 90-nm-thick silicon layer, the advantages of the two-dimensional confinement effect are shown.

Effect of e‐beam irradiation on a p‐n junction GaN light emitting diode

Abstract: A GaN p‐n junction structure was grown on a (0001) sapphire substrate by atmospheric pressure metalorganic chemical vapor deposition using a double buffer layer. The resulting light emitting diode (LED) was further exposed to a low‐energy electron beam source. The effect of e‐beam exposure on the room‐temperature electroluminescence spectra of the LED is reported. It is found that the electroluminescence spectral features change dramatically as a function of the electron‐beam exposure time and current density. This is attributed to changes in active Mg concentration. The origin of each electroluminescence band is discussed.

Two-dimensionally confined injection phenomena at low temperatures in sub-10-nm-thick SOI insulated-gate p-n-junction devices

Abstract: This paper describes two-dimensionally confined carrier injection phenomena in thin-SOI insulated-gate pn-junction devices fabricated on SIMOX substrates. At 28 K conductance shows step-like anomalies due to the manifestation of a two-dimensional subband system in an 8-nm-thick-SOI structure at a low gate bias. Conductance shows an oscillation-like feature at a high gate bias because of the injection mode change. These effects are examined by theoretical simulations based on quantum mechanics.

Lateral Tunneling Devices on GaAs (111)A and (311)A Patterned Substrates Grown by MBE Using Only Silicon Dopant

Abstract: A lateral interband tunneling transistor with gate-controlled negative differential resistance characteristics is demonstrated for the first time on a GaAs(111)A patterned substrate. Si-doped GaAs layers are grown on GaAs(111)A and GaAs(311)A patterned substrates by molecular beam epitaxy to fabricate lateral p-n junctions. Both samples show interband tunneling diode characteristics. Furthermore, a gate electrode is fabricated on the (111)A sample. The lateral tunneling transistor shows a modulated peak current density that ranges from 0.41 to 0.90 mA/cm 2 by varying the gate voltage from -5.0 to 5.0 V at 77 K.

Planar P-N junction semiconductor structure with multilayer passivation

Abstract: A semiconductor device, which has a silicon body that includes at least one planar p-n junction that intersects a surface of the body, uses a multilayer arrangement that includes a first layer of thermally grown silicon dioxide, a second layer of Chemical-Vapor-Deposited (CVD) silicon nitride, a third layer of CVD oxygen-rich polysilicon, and a fourth layer of CVD silicon dioxide to passivate the junction. Common metallization contacts both the diffused region of the planar junction and the oxygen-rich polysilicon.

Resistless, area-selective ultrashallow p+/n junction fabrication using projection gas immersion laser doping

Abstract: The selective fabrication of ultrashallow p+/n junctions in silicon using projection gas immersion laser doping is reported. The method offers substantial improvement and simplification in junction formation to integrated circuit manufacturers, since several processing steps required for conventional doping techniques like ion implantation are eliminated. Spatially selective incorporation of boron into silicon without the use of any masking layer on the wafer surface is achieved. A pulsed excimer laser beam is patterned using a chromeless reticle and the pattern is transferred through a projection system onto a wafer that is kept in a BF3 dopant gas ambient. The depth of the fabricated junctions is 60 nm with a surface concentration of 5×1019 cm−3. The vertical and lateral distribution of boron in silicon after patterned laser processing is investigated using secondary ion mass spectroscopy (SIMS) and time‐of‐flight SIMS (ToF‐SIMS). Vertical and lateral dopant profiles are steep and clearly resolved.