Showing papers on "Pass transistor logic published in 1997"

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Pass-transistor adiabatic logic using single power-clock supply

Abstract: We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Abstract: This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance,.

Single-electron logic device based on the binary decision diagram

Abstract: The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly.

Logic synthesis for large pass transistor circuits

Abstract: Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

System-on-chip layout compilation

Abstract: A layout compiler compiles from hardware description language (HDL) and schematic description of a design, which consists of dynamic random access memory (DRAM) components and logic components, to the layout of an integrated logic and DRAM system on a single integrated chip. The layout compiler creates the physical structure (floor-plan) of integrated logic/DRAM chips and generates on-chip interconnections between the DRAM components and logic components. By integrating logic and DRAM memory onto the same chip, the performance gap which is the difference between the logic processor's data processing rate and the DRAM memory's data access rate can be minimized. Further, the bandwidth between the logic processor and the DRAM memory can be increased significantly. The layout methods eliminate the off-chip drivers and heavy capacitive loads presented in the off-chip interconnections. Low power dissipation is a direct result of integrated logic/DRAM chip in high frequency operations. This method enables the optimization of the on-chip metal interconnections between the logic components and the DRAM components in a way to achieve higher system bandwidth and system performance, lower power dissipation and packaging cost.

Semiconductor memory device

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption and to speed operation by reducing the consumed current flowing in bit lines and also the loading capacity connected to the bit lines SOLUTION: The bit line BL0 is divided into four bit lines, and the divided bit lines BL0A-BL0D are respectively connected to four memory blocks A-D composed of plural memory cells, pass transistors 1-4 and precharge transistors 5-8 When a memory block A is selected by an address, the corresponding pass transistor 1 alone is turned on and the pass transistors 2-4 of the other memory blocks are turned off Furthermore only the precharge transistor 5 of the memory block A is turned off, and the precharge transistors 6-8 of the other memory blocks are kept on to hold the precharge state and read the data out from the selected memory block

A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders

Abstract: A 54/spl times/54-b multiplier with only 60 K transistors has been fabricated by 0.25-/spl mu/m CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54/spl times/54-b multiplier is 1.04/spl times/1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply.

Floating-body effects in partially depleted SOI CMOS circuits

Abstract: This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Redundancy circuitry for logic circuits

Abstract: Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

A low-power design method using multiple supply voltages

Abstract: We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of "Clustered Voltage Scaling (CVS) scheme" and "Row by Row optimized Power Supply (RRPS) scheme". By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called "RRPS scheme" is proposed. The proposed method is applied to a media processor chip Mpact/sup TM/ and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply-voltage gates. The clocking scheme for the multiple supply voltages is also discussed.

Decision Diagrams and Pass Transistor Logic Synthesis

Abstract: Since the relative importance of interconnections increases as feature size decreases, standard-cell based synthesis becomes less effective when deep-submicron technologies become available. Intra-cell connectivity can be decreased by the use of macro-cells. In this work we present methods for the automatic generation of macro-cells using pass transistors and domino logic. The synthesis of these cells is based on BDD and Z BDD representations of the logic functions. We address specific problems associated with the BDD approach (level degradation, long paths) and the Z BDD approach (sneak paths, charge sharing, long paths). We compare performance of the macro-cells approach versus the conventional standard-cell approach based on accurate electrical simulation. This shows that the macro-cells perform well up to a certain complexity of the logic function. Functions of high complexity must be decomposed into smaller logic blocks that can directly be mapped to macro-cells.

Fast adders using enhanced multiple-output domino logic

Abstract: Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-/spl mu/m CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path.

Digital logic design using negative differential resistance diodes and field-effect transistors

Abstract: A digital logic gate circuit including a logic block, clock transistor, bias transistor and a negative differential resistance (NDR) diode which acts as an active load for the circuit. The logic block, comprising a plurality of field effect transistors whose control terminals receive the set of input signals to the logic gate, determines the gate function such as inversion, NAND, NOR, MAJORITY, etc. The clock transistor is connected in series with the logic block and the bias transistor is connected in parallel across this series combination. The terminal of the NDR diode affixed to the common terminal of the bias transistor and the logic block forms the output for the logic circuit. NDR diodes include but are not limited to devices such as tunnel diodes and resonant tunneling diodes (RTDs). The folded I-V characteristic of an NDR diode allows the circuits to operate in a bistable clocked mode, where the circuit output latches its state and changes only when the clock signal is active. The circuit topology allows logic functions to be implemented in a compact manner, thus reducing the propagation delay for the signals, and reducing the overall complexity and delay of arbitrary logic circuits. Thus, performance improvements result from the compactness of logic design as well as the elimination of a pipeline latch area and delay overheads.

Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating same

Abstract: Integrated circuit memory devices contain a plurality of nonvolatile memory cells and preferred circuits for selectively configuring the memory cells as multi-bit memory cells having more than two programmable states, during a multi-bit mode of operation, or for configuring the memory cells as single-bit memory cells during a single-bit mode of operation. The preferred circuits contain first and second sense amplifiers that can be electrically coupled to first and second strings of memory cells in the plurality thereof, and a pass transistor for electrically connecting sense nodes of the first and second sense amplifiers together during the multi-bit mode of operation. The first and second sense amplifiers also contain first and second latches, respectively, and the first and second latches each have normal and complementary outputs. The normal outputs of the first and second latches are electrically coupled to first and second input/output lines, respectively. First and second latch control circuits are also provided for enabling the single-bit and multi-bit modes of operation. Here, the single-bit mode of operation (i.e., two-state mode of operation) may be used for high fidelity applications requiring fault-free operation and the multi-bit mode of operation (e.g. four-state mode of operation) may be used for applications involving the storage of mass amounts of information such as audio data, where memory loss or corruption of small amounts of data does not significantly affect the fidelity of the information when read as a whole.

Real time parser for data packets in a communications network

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Resonant-tunneling transmission line technology

Abstract: Resonant-tunneling transmission lines in the various architectures rely on discrete or continuous resonant-tunneling heterostructures to actively modify propagating logic signals. One embodiment utilizes amplification of logic signals to counteract ubiquitous losses and distortion associated with any transmission medium. Basically, the logic signal is incrementally reamplified and reshaped as it propagates along the transmission line. Another embodiment is directed to a clocking system that transmits a signal represented by a sinusoid. Then, in proximity to the logic gates or modules, the sinusoid is converted into a square wave that actually clocks the gates and other logic structures. The inventive active transmission line naturally performs this feature, thus enabling clock signal transmission over longer links coupled with sinusoid-to-square wave conversion in a limited area. Still other embodiments implement step or continuous variations in the physical width of the resonant-tunneling transmission line. By manipulating the transmission line width of successive sections of the line, isolation in addition to the logic operation of the input signals is achievable in a simple monolithic circuit design. Further embodiments are directed to oscillator circuits and the control of the characteristics of the generated periodic signal.

System and method for a low voltage charge pump with large output voltage range

Abstract: A low voltage charge pump system with a large output voltage range is described. The charge pump system comprises eight charge pump stages, an output stage, and a four phase clock generator. The clock generator generates two sets of four phase shifted signals. The first set of four clock signals are coupled to the first four charge pump stages and have a logic high level of VCC. The second set of clock signals are coupled to the second four charge pump stages and have a logic high level of 2 VCC. Due to the body effect, the negative voltages at the charge pump output stages increases the threshold voltage of a pass transistor which couples the input and output in each charge pump. The larger high voltage level of the second set of clock signals enables the signals to overcome the body effect increased threshold voltages of the pass transistors. The pass transistors are then used to couple negative charge to the next charge pump stage, and positive charge to the preceding charge pump stage. The present invention charge pump system can thereby provide a large negative voltage output using a low power supply voltage. In the charge pump stages that receive the higher clock levels and in the output stage, the well of capacitor configured PMOS transistors that are coupled to the stage clock terminals is coupled to the source and drain of the transistors. Coupling the source, drain and well together prevents the 2 VCC voltage high level clock signals from forward biasing the p-n junction formed by the source and drain with the well. The charge pump stages and the output stage also include a p-n junction diode coupled from the output of the stage to ground.

Single-transistor logic and CMOS inverters

Abstract: A dual transistor CMOS inverter can be built wherein a single gate is shared by two MOS transistors but only one transistor can be turned on at a time. A CMOS inverter function is provided. Further, a dual transistor logic function is described incorporating a combination of a lateral bipolar transistor (LBT) and a metal-oxide-semiconductor transistor (MOST). The gate of the MOST is used to turn on and off the base of the LBT. When the base is turned on, the LBT is turned on and off depending on the base voltage. This device has, thus, two inputs and can perform logic functions such as OR or NAND, which would typically require four transistors. The invention solves the problem of device density to perform logic by forming stacked devices with shared electrodes.

1.8 volt output buffer on flash memories

Abstract: A high-speed output buffer for a nonvolatile writeable memory is described. The high-speed output buffer receives signals from the nonvolatile writeable memory having a pair of logic levels. The high-speed output buffer provides output signals having a pair of logic levels that may differ from the pair of logic levels of the signal received from the nonvolatile writeable memory. The high-speed output buffer comprises two inverters, a pull-up device, and a circuit with a relatively low voltage drop. The circuit with the relatively low voltage drop causes the high-speed output buffer to receive signals having one pair of logic levels while providing high-speed output signals having another pair of logic levels which may differ from the pair of logic levels of the received signal. The high-speed output buffer is coupled to a different power supply output from the nonvolatile writeable memory. The high-speed output buffer uses input and output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.

Low-power CMOS design through V/sub TH/ control and low-swing circuits

Abstract: This paper describes some of the circuit level techniques for low-power CMOS designs. V/sub TH/ control circuits are necessary for achieving low-threshold voltage in high-speed low-voltage applications. As for the low swing circuit techniques, applications to a clock system, logic part, and I/O's are discussed.

Fuse option for multiple logic families on the same die

Abstract: A chip's interface is selected by using a fuse option coupled between integrated circuitry on the chip and logic circuitry. Fuse options correspond to antifuses or fuses. In one embodiment, a plurality of fuse options are manufactured in an integrated circuit such that a fuse option is coupled between integrated circuitry on the chip and separate and complete logic circuitry for different logic types used to interface a chip. In another embodiment, only one type of logic circuitry is manufactured on a chip, such that the logic circuitry has both a pull-up and pull-down transistor. A fuse is coupled with a pull-up control circuit of the logic circuitry. When the fuse is blown, the output circuit corresponds to GTL-terminated logic circuitry, using only the pull-down transistor. In a further embodiment, an antifuse is coupled with the pull-up control circuit. When the antifuse is programmed, default GTL-terminated logic is converted to TTL family output logic, or another logic which uses both pull-up and pull-down transistors in its logic circuitry.

Logic synthesis for large pass transistor circuits

Abstract: Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multistage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. They show that the proposed approach allows one to make logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do nor have any equivalent in the traditional approach. They also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that the technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of their knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

Circuitry for emulating asynchronous register loading functions

Abstract: Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

Programmable logic integrated circuit architecture incorporating a lonely register

Abstract: A logic element for a programmable logic device to implement a lonely register architecture. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

A new SOI inverter using dynamic threshold for low-power applications

Abstract: A new SOI inverter using the dynamic threshold (DT) that lowers threshold voltage of MOSFET only in active operation of a logic circuit is proposed for high-speed and low-power applications. The dynamic threshold scheme is realized by dynamically biasing the body of MOSFET's. The SOI MOSFET's have been designed and fabricated to take full advantage of the reverse body effect which is affected by many device parameters. From the measurements and simulations, the proposed scheme is shown to be useful in the buffer with large load conditions and low supply voltage if the SOI MOSFET's are properly designed.

Field Programmable Logic Gates Using GMR Devices

Abstract: This paper summarizes the basic methodology for building field programmable logic functions using GMR devices. The size of the gates and the properties of the sense amplifier are a function of the particular GMR technology used, device matching and the magnitude of the sense current available. A test chip is currently in fabrication.

Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits

Abstract: Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops. These Domino scan flip-flops can be used in the Domino logic as sequential elements to allow a multiplicity of logic functions to be implemented using Domino logic. These scan flip-flops can then be serially connected either as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. These Domino scan flip flops allow all of the nominal logic to be tested in conjunction with the two registers. A relationship between a Domino clock that is used to drive the Domino logic in a system clock that is used to drive the static CMOS logic is described which ensures that a correct test data is applied and read out from the hybrid circuit.