Showing papers on "Phase detector published in 2011"

Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation

Abstract: During the grid synchronization of distributed generation (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect grid phase angle. Conventional PLL schemes used in DG controller have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To simultaneously realize good steady-state and transient performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored to eliminate any specified harmonic. The proposed DSC operator can be further cascaded to stepwise reject all undesired harmonics. Then the conditioned voltage signal can be used in PLL loop to achieve fast transient response at high control bandwidth without suffering from the steady-state error caused by harmonics. Based on differently configured DSC operators, two PLL designs are then developed, namely CDSC-PLL1 and CDSC-PLL2. Specifically, CDSC-PLL1 is aimed for grid voltage with unbalance and odd/even harmonics, while CDSC-PLL2 further addresses asymmetrical harmonics, i.e., harmonics arising from asymmetrically distorted three-phase voltages. By introducing a frequency feedback loop, the proposed PLL can operate properly during considerable frequency variations, even when a phase jump or severe harmonics are also present. All proposed PLL designs have very simple structure and can be easily implemented. The superior performance is confirmed by experimental results.

Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems

Abstract: A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.

Wireless power feeder, wireless power receiver, and wireless power transmission system

Abstract: Power is fed from a feeding coil L2 to a receiving coil L3 by magnetic resonance. A VCO 202 alternately turns ON/OFF switching transistors Q1 and Q2 at a drive frequency fo, whereby AC power is fed to the feeding coil L2, and then the AC power is fed from the feeding coil L2 to the receiving coil L3. A phase detection circuit 114 detects a phase difference between the current phase and voltage phase, and the VCO 202 adjusts the drive frequency fo such that the phase difference becomes zero. When load voltage is changed, the detected current phase value is adjusted with the result that the drive frequency fo is adjusted.

Running DFT-Based PLL Algorithm for Frequency, Phase, and Amplitude Tracking in Aircraft Electrical Systems

Abstract: Phase-locked loop (PLL) algorithms are commonly used to track sinusoidal components in currents and voltage signals in three-phase power systems. Despite the simplicity of those algorithms, problems arise when signals have variable frequency or amplitude, or are polluted with harmonic content and measurement noise, as can be found in aircraft ac power systems where the fundamental frequency can vary in the range 360-900 Hz. To improve the quality of phase and frequency estimates in such power systems, a novel PLL scheme based on a real-time implementation of the discrete Fourier transform (DFT) is presented in this paper. The DFT algorithm calculates the amplitudes of three consecutive components in the frequency domain. These components are used to determine an error signal which is minimized by a proportional-integral loop filter in order to estimate the fundamental frequency. The integral of the estimated frequency is the estimated phase of the fundamental component, and this is fed back to the DFT algorithm. The proposed algorithm can therefore be considered to be a PLL in which phase detection is performed via a DFT-based algorithm. A comparison has been made of the performances of a standard PLL and the proposed DFT-PLL using computer simulations and through experiments.

Fixed-Reference-Frame Phase-Locked Loop for Grid Synchronization Under Unbalanced Operation

Abstract: This paper presents a grid synchronization scheme aimed to provide an estimation of the angular frequency and both the positive and negative sequences of the fundamental component of an unbalanced three-phase signal. These sequences are provided in fixed-reference-frame coordinates, and thus, the proposed algorithm is referred to as fixed-reference-frame phase-locked loop (PLL) (FRF-PLL). In fact, the FRF-PLL does not require transformation of variables into the synchronous frame coordinates as in most PLL schemes. Therefore, the proposed scheme is not based on the phase angle detection. Instead, the angular frequency is detected and used for synchronization purposes. The design of the FRF-PLL is based on a complete description of the source voltage involving both positive and negative sequences in stationary coordinates and considering the angular frequency as an uncertain parameter. Therefore, the FRF-PLL is intended to perform properly under severe unbalanced conditions and to be robust against angular frequency variations, sags, and swells in the three-phase utility voltage signal. Due to the selective nature of the scheme, it shows certain capability to alleviate the effect of harmonic distortion that is present in the utility voltage signal.

Led drive circuit, dimming device, led illumination fixture, led illumination device, and led illumination system

Abstract: An LED drive circuit in which an alternating voltage from a phase control dimmer is input and an LED is driven The LED drive circuit comprises a phase angle detector for detecting the phase angle at which a phase control element inside the phase control dimmer switches from off to on; a switching power supply for feeding a current to the LED; a switching element connected in series to the LED; and a controller for controlling the switching power supply and the switching element in accordance with the output of the phase angle detector; wherein the controller places the switching element in an always-on state in a case in which the phase angle detected by the phase angle detector is equal to or less than a predetermined value, and the controller pulse-drives the switching element in a case in which the phase angle detected by the phase angle detector is greater than the predetermined value

An Efficient Approach to Correct the Signals and Generate High-Resolution Quadrature Pulses for Magnetic Encoders

Abstract: A magnetic encoder (ME) is a kind of sinusoidal encoder using magnetic effects that is currently utilized in many industrial control systems because it has many advantageous characteristics: low cost, simple structure, works in harsh environments, high reliability, and so on. The signals generated by an ME are always disturbed by noises; therefore, these signals are not ideal. The challenge is to achieve the highest resolution and to get the maximum operating speed as well as to use the most cost-effective hardware. To solve this problem, this paper humbly proposes an effective approach, which contains two parts: The main part is “compensating the noisy signals of MEs” by applying a new proposed method called the advanced adaptive digital phase-locked loop (AADPLL), while the second is a pulse interpolator which generates high-resolution quadrature pulses. The AADPLL algorithm provides a robust filtering characteristic to eliminate the noises and improve the accuracy of the ME's input signals. It also takes advantage of tracking high-speed input signals without time lag, unlike the traditional filters. Additionally, the computation burden is significantly reduced in this algorithm to allow it to be easily implemented in a low-cost processor. The pulse interpolator is based on an existing idea that extracts high-order sinusoids from the original ME signals. However, a new scheme is presented to achieve higher resolution per period with smaller noises affecting the output pulses. Both parts are mainly implemented in a unique hardware platform using a low-cost digital signal processor, such as the TMS320F2812, combined with a small-size field-programmable gate array. This method has already been applied to control a linear motor without using an expensive optical linear encoder. Practical results are provided to demonstrate the effectiveness of the proposed method.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Abstract: We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Graphene Ambipolar Multiplier Phase Detector

Abstract: We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of -7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude.

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS

Abstract: High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block. Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over >;13 GHz bandwidth, -22.5 dBc integrated phase noise while consuming 84 mW.

Analysis and Design of a Digital Phase-Locked Loop for Single-Phase Grid-Connected Power Conversion Systems

Abstract: A new digital phase-locked-loop (DPLL) method is proposed for single-phase grid-connected power conversion systems in this paper The analysis of a phase detector using trigonometric function transformation is presented in detail A sliding-window-based data sampling method is utilized to obtain the orthogonal signal related to the original input signal according to the periodic characteristic of the steady-state sine fundamental component, and the fictitious active and reactive power components are constructed On this basis, the DPLL method is developed It consists of an even harmonics elimination network, a grid voltage feedforward network, and a fictitious instantaneous power feedback phase correction network The fundamental signal of the grid voltage is extracted by an even harmonics elimination network and a digital Butterworth filter and a unit value controller to generate a unity sine reference signal for the feedforward network, whereas only the signs of the fictitious instantaneous active and reactive powers are used to revise the phase shift of the unity sine reference signal by means of a real-time variable step-size control in the feedback phase correction network The method is validated to have good dynamic and static performances through MATLAB simulations, simulator investigations, and experiments with a grid-connected photovoltaic system under different voltage conditions

A review on fundamental grid-voltage detection methods under highly distorted conditions in distributed power-generation networks

Abstract: In distributed power generation systems a fast and accurate positive-sequence fundamental grid-voltage frequency and magnitude tracking is required to synchronize grid-connected converter-systems with the mains. In this paper state-of-the-art fundamental grid-voltage detection methods based on the extension of the Synchronous Reference-Frame phase-locked loop with either an additional pre-filter for the phase detection or an extended loop-filter are presented and compared to each other. The performance of these methods is studied in the laboratory environment during harmonic voltage-distortions as well as characteristic grid-faults. Furthermore, a new approach using a combined pre- and extended loop-filter technique to improve the harmonic voltage-distortion rejection abilities is presented and thoroughly verified by measurements. The analysis reveals that the optimal choice of the PLL-methods is a trade-off between the dynamic performance requirements and the accuracy of the grid-voltage tracking during highly distorted grid-conditions. Furthermore, the proposed combined filter approach reveals fast voltage tracking performance with good voltage distortion rejection abilities.

A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters

Abstract: For grid-connected power converters, the frequency and phase angle of the grid voltage, which are essential to the system operations, must be quickly and accurately obtained even if the utility voltage is distorted or unbalanced. In this paper, a novel hardware-based all-digital phase-locked loop (ADPLL) is proposed for grid interface converters to detect the frequency and phase angle based on the voltage zero crossings. The proposed ADPLL features wide track-in range and fast pull-in time, and it can easily be integrated with the digital controller for grid-connected power converters. A discrete small-signal model is presented to investigate the performance and parameter dependence of the ADPLL. As expected, the output phase error and pulse jitter are minimized by selecting a high clock frequency and proper regulator parameters. With additional voltage sensors, the ADPLL can be readily extended into applications with grid disturbances. Experimental results verify the analysis and the effectiveness of the ADPLL.

Frequency synthesizer and frequency synthesizing method

Abstract: The present invention relates to a frequency synthesizer comprising a main unit and a side unit The main unit comprises a main phase detector to obtain a main control signal, a main oscillator that generates a main synthesized frequency output signal representing the frequency synthesizer output signal based on said main control signal, and a mixer that mixes said main synthesized frequency output signal with a side synthesized frequency output signal to obtain said mixer output signal The side unit generates said side synthesized frequency output signal and comprises a frequency signal generation unit that provides a linear frequency sweep signal or a fixed-frequency control signal at a fine frequency resolution from said fixed-frequency side reference signal, and a side oscillator that generates said side synthesized frequency output signal based on said frequency sweep signal or said fixed-frequency control signal

Phase identification system and method

Abstract: A phase identification system (70) includes a power distribution station (12) and a phase detection device (140). The power distribution station (12) includes a phase distortion device (72) for generating voltage distortions of a known harmonic frequency in at least one of three phase voltage signals of the power distribution station (12). The phase detection is configured to receive at least one of distorted three phase voltage signals and to identify a phase of the received voltage signal. The phase detection device (140) includes a delay circuit (144) to generate a phase shifted voltage signal of the received voltage signal and a transformation module (142) to transform the received voltage signal and the phase shifted voltage signal into d-q domain voltage signals of a known harmonic frequency reference frame. A phase determination module (154) in the phase detection device (140) determine the phase of the received voltage signal by comparing an amplitude of a harmonic of the known harmonic frequency in the received voltage signal with a threshold value.

A novel dispersion and PMD tolerant clock phase detector for coherent transmission systems

Abstract: A novel clock phase detector is presented and shown to be tolerant to chromatic dispersion and PMD. The phase detector can be used in a clock recovery circuit for demodulation of 100 Gb/s coherent transmission system.

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

Abstract: In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of the digitally controlled oscillator (DCO) so as to further reduce the phase error and jitter. Simulation results show that the jitter performance is very close to that of the free-running DCO. Measurement results show that the jitterPk-Pk and jitterRMS are 56 and 7.28 ps, respectively, when the output clock of the ADPLL is running at 600 MHz.

A comparative analysis and implementation of various PLL techniques applied to single-phase grids

Abstract: The scope of this work is to find the best approach to control advanced inverters used to connect electric vehicles to the grid. Phase-locked Loop (PLL) is a grid voltage phase detection that makes use of an orthogonal voltage to lock the grid phase. This method is suitable for both single and three phase systems, although in single-phase, because they have less information, more advanced systems are required. The easiest way to obtain the orthogonal voltage system is using a transport delay block to introduce a phase shift of 90 degrees with respect to the fundamental frequency of the grid voltage. This method is known as Synchronous Reference Frame PLL (SRF-PLL). The use of inverse Park transformation is also possible. To lower the complexity and increasing the filtering of the output signals, methods using adaptive filters are a good alternative. For this approach, the use of a second order generalized integrator (SOGI) or Adaptive Notch filter combined with PLL, Enhanced PLL (EPLL) and Quadrature PLL (QPLL), leads to satisfactory results.

Phase drift cancellation of remote radio frequency transfer using an optoelectronic delay-locked loop.

Abstract: In this Letter, we propose a phase drift cancellation method for remote radio frequency transfer. Phase fluctuation along the transmission fiber, which is induced by temperature and pressure changes, is measured and compensated by a heterodyne optoelectronic delay-locked loop. The control loop consists of a heterodyne optoelectronic phase detector, a microwave delay module, and the loop filter. We demonstrate the concept by transmitting a 10 GHz microwave frequency over 50 km single-mode fiber, with subpicosecond jitters measured at the remote end.

Synthetic ripple regulator with frequency control

Abstract: A synthetic ripple regulator including frequency control based on a reference clock. The regulator includes an error network, a ripple detector, a combiner, a ripple generator, a comparator network and a phase comparator. The error network provides an error signal indicative of relative error of the output voltage. The ripple detector provides a ramp control signal based on the input and output voltages and a pulse control signal. The combiner adjusts the ramp control signal based on a frequency compensation signal to provide an adjusted ramp control signal. The ripple generator develops a ripple control signal based on the adjusted ramp control signal. The comparator network develops the pulse control signal to control switching based on the error signal and the ripple control signal. The phase comparator compares the pulse control signal with the reference clock and provides the frequency compensation signal.

Phase-lock loop-based clocking system, methods and apparatus

Abstract: In part, the invention relates to an optical coherence tomography system that includes one or more phased-locked loop circuits. In one embodiment, the phased-locked loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator wherein the phased-locked loop circuit is configured to generate a sample clock. The optical coherence tomography system can include an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. In one embodiment, the phased-locked loop circuit is configured to lock on a first signal in less than or equal to about 1 microseconds.

Monolithically integrated heterodyne optical phase-lock loop with RF XOR phase detector

Abstract: We present results for an heterodyne optical phase-lock loop (OPLL), monolithically integrated on InP with external phase detector and loop filter, which phase locks the integrated laser to an external source, for offset frequencies tuneable between 0.6 GHz and 6.1 GHz. The integrated semiconductor laser emits at 1553 nm with 1.1 MHz linewidth, while the external laser has a linewidth less than 150 kHz. To achieve high quality phase locking with lasers of these linewidths, the loop delay has been made less than 1.8 ns. Monolithic integration reduces the optical path delay between the laser and photodiode to less than 20 ps. The electronic part of the OPLL was implemented using a custom-designed feedback circuit with a propagation delay of ~1 ns and an open-loop bandwidth greater than 1 GHz. The heterodyne signal between the locked slave laser and master laser has phase noise below −90 dBc/Hz for frequency offsets greater than 20 kHz and a phase error variance in 10 GHz bandwidth of 0.04 rad2.

Design of a photonic crystal differential phase comparator for a Mach-Zehnder switch

Abstract: In this paper a novel photonic crystal (PC) phase comparator is proposed. The proposed structure can be used in a PC Mach?Zehnder as the signal adder section to improve its performance. The phase comparator provides an approximately 15?dB contrast ratio for the wavelength range of 1545?1555?nm. The finite difference time domain method and plane wave expansion method are used to evaluate the structure.

Method and apparatus for implementing EIT magnetometry

Abstract: A magnetometer is provided comprising an atomic vapor in an enclosure, a source of light for preparing the vapor into a state exhibiting electromagnetically induced transparency, a first laser beam passing through the atomic vapor, a phase detector for detecting changes in phase of the first laser beam, and a controller which controls the light source and laser beam and receives the information detected by the phase detector in order to compute from those changes in phase a magnetic field strength in the presence of a selected background magnetic field of at least 0.001 T. Operation in the presence of a background field helps make this magnetometer suitable for diagnostic imaging applications.

Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

Abstract: We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter.

A 300 GHz PLL in an InP HBT technology

Abstract: Summary form only given, as follows. We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2∶1 dynamic frequency divider, 5th-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with −23 dBm of output power and −78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm2 including pads. This work represents the highest frequency PLL reported thus far, 2× to 3× faster than previously reported PLLs.

Measuring unit for use in measuring system for telemetric evaluation of electrical oscillating circuit, has phase detector determining phase difference between electrical reference oscillation and electrical measuring oscillation

Abstract: The measuring unit (1) has a vibration source (3) for generating electrical reference oscillation in a reference branch (6) and electrical measuring oscillation in a measuring branch (7). A coupling coil (4) is arranged in the measuring branch and inductively coupled to a resonant circuit coil (21) of sensors (20). A phase detector (5) taps the reference oscillation at the reference branch and the measuring oscillation at the measuring branch. The phase detector determines phase difference between the reference oscillation and the measuring oscillation.

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

Abstract: A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER <; 10-12) for PRBS data sequences ranging from 27 - 1 to 231-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.

Motor drive control device and method

Abstract: PROBLEM TO BE SOLVED: To make use of a motor commutation drive magnetic sensor to perform more phase detection than otherwise possible, without using an expensive optical encoder.SOLUTION: In a motor drive control device, a phase information signal to control motor drive is generated on the basis of a plurality of sensor signals having a signal level corresponding to the rotation position of the rotor of a motor. The plurality of sensor signals are compared with a plurality of prescribed threshold levels to detect a phase, and a first phase information signal indicating the detected phase is output. The plurality of sensor signals are compared with each other to detect a phase, and a second phase information signal indicating the detected signal is output. The detected phases included in the first and the second phase information signals are divided into a plurality of prescribed phase sections. In the plurality of prescribed phase sections, one of a plurality of sensor signals is selected, and detection is made to see that the signal level of the selected sensor signal has reached a prescribed threshold level corresponding to a prescribed phase of the rotor, whereby a phase information signal indicating the detected phase is output.