Showing papers on "Polycrystalline silicon published in 1997"

Field effect-controlled semiconductor component

Abstract: The claimed field effect-controlled semiconductor component has a drain zone of the first conduction type, at least one gate electrode made of polycrystalline silicon and insulated from the drain zone, and a source region of the second conduction type built into the drain zone. In addition, a trench structure is also formed in the drain zone; this can extend from the surface of the epitaxial layer down to the substrate layer, and contains an additional polysilicon magnetoresistor embedded in an oxide layer. The oxide surrounding the polysilicon magnetoresistor increases in thickness vertically towards the drain.

Silicon dioxide sacrificial layer etching in surface micromachining

Abstract: Silicon dioxide sacrificial layer etching has become a major surface micromachining method to fabricate microsensors and microactuators often made of polycrystalline silicon. An overview of the materials available in integrated circuit manufacturing is given, and the etch mechanism and sacrificial layer etch kinetics are reviewed. Selectivity issues important for the proper choice of layers and etchants are addressed discussing the chemical attack of aluminum during long sacrificial layer etching, as an example. Various etchants known from other studies are compared: concentrated and dilute HF, buffered HF (BHF), nitric acid based etchants known as P-etch, R-etch, S-etch, as well as mixtures of HF and HCl, and vapor HF. `Pad-etch', an acetic acid/ammonium fluoride/ethyleneglycole solution is shown to have an enhanced selectivity against aluminum. Some device examples such as arrays of deflectable micromirrors demonstrate the versatile application of sacrificial oxide etching in surface micromachining.

Floating body effects in polysilicon thin-film transistors

Abstract: Floating body effects in polycrystalline silicon thin film transistors (poly-TFTs) are investigated by means of numerical simulations. The current increase in the output characteristics at large V/sub DS/, usually referred to as the "kink effect" is explained by impact ionization occurring in the high-field region at the drain end of the channel. Its effect is enhanced by the action of a parasitic bipolar transistor in the back-channel region, whose base current arises from the impact generated holes. The dependence of the kink on the recombination kinetics is also investigated.

Device-quality polycrystalline and amorphous silicon films by hot-wire chemical vapour deposition

Abstract: We describe how high-quality intrinsic hydrogenated amorphous silicon (a-Si: H), as well as purely intrinsic single-phase hydrogenated polycrystalline silicon (poly-Si: H), can be obtained by hot-wire chemical vapour deposition (HWCVD). The deposition parameter space for these different thin-film materials has been optimized in the same hot-wire deposition chamber. A review of the earlier work shows how such high-quality films at both ends of the amorphous-crystalline scale have evolved. We incorporated both the amorphous and the polycrystalline silicon films in n-i-p solar cells and thin-film transistors (TFTs). The solar cells, with efficiencies in excess of 3%, confirm the material quality of both the a-Si: H and the poly-Si: H i-layer materials, but more work is needed to improve the interfaces with the doped layers. The TFTs made with a-Si: H and poly-Si: H channels show quite similar characteristics, such as a field-effect mobility of 0·5cm2 V−1 s−1, indicating that the channel region has a...

Manufacture of semiconductor integrated circuit device

Abstract: PURPOSE: To improve the degree of integration of the title device and to contrive accomplishment of high speed operation of the device by a method wherein impurities are introduced into the main surface of the substrate located under the first layer gate electrode through the first layer gate electrode, information is written, and the second layer and the third layer gate electrodes are formed alternately between the first gate electrodes. CONSTITUTION: Before the writing of information into the first layer gate electrode 5, impurities 7a are introduced after a mask 19 has been formed on the upper part of the first layer gate electrode 5. To be more precise, on the polycrystalline silicon layer which is used for formation of the gate electrode 5 deposited on the whole surface of a substrate, a silicon oxide film to be formed by performing a CVD method and the like, for example, and a silicon nitride film are additionally formed. Then, these insulating film and polycrystalline silicon are etched successively by performing the anisotropic etching such as an RIE and the like, and the first layer gate electrode 5 and a mask 19 are formed. The mask 19 is formed on the upper part of the first layer gate electrode 5 in a self-matching manner, impurities 7a are introduced through both of them, and information is written under the first gate electrode 5. Consequently, as the implanting energy of impurities 7a can be made larger by the mask 19, the sufficient positional difference of the impurities 7a to be introduced under the first and the second layer gate electrodes 5 and 9 can be secured (the difference of positions is made larger). COPYRIGHT: (C)1988,JPO&Japio

Effect of hydrogen termination on the work of adhesion between rough polycrystalline silicon surfaces

Abstract: A novel micromachined test structure has been used to measure the work of adhesion between polycrystalline silicon surfaces. The effects of several surface treatments, including a hydrogen- and an ammonium-fluoride-induced hydrogen termination and a hydrogen peroxide chemical oxidation, have been investigated with these test structures. A reduction in the average apparent work of adhesion by a factor of 2000 has been observed on the NH4F-treated surface compared to the oxide-coated surface. By using x-ray photoelectron spectroscopy and atomic force microscopy, the observed reduction is traced to the combined effect of the surface chemistry and topography. This work demonstrates that a hydrophobic, rough surface provides a significant reduction of the apparent work of adhesion in polysilicon micromachined devices.

Stiction reduction processes for surfacemicromachines

Abstract: We present a review of surface micromachining technology with anemphasis on polycrystalline silicon (polysilicon)microstructures. The problems of release-related and in-usestiction are then introduced along with a brief review ofvarious approaches developed for reducing them. These includesurface roughening and chemical modification of the siliconsurfaces. The constraints that post-release back-end processessuch as assembly and packaging place on surface treatments aredescribed in general. Finally, we briefly outline some of theimportant scientific and technological issues that remain to be clarified in stiction phenomena in micromechanical structures.

Metal-oxide-semiconductor capacitors formed by oxidation of polycrystalline silicon on sic

Abstract: A method to form SiO2/SiC metal–oxide–semiconductor structures by oxidation of a thin polycrystalline silicon (polysilicon) layer deposited on SiC is demonstrated. The oxidation time used is sufficient to oxidize all the polysilicon while short enough at 1050 °C to insure insignificant oxidation of the underlying SiC. Since the oxidation of SiC is highly anisotropic, this method allows uniform oxide formation on a nonplanar SiC surface. The SiO2/SiC interface quality is comparable to that obtained with thermal oxidation.

Effects of NH/sub 3/ plasma passivation on N-channel polycrystalline silicon thin-film transistors

Abstract: The NH/sub 3/-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH/sub 3/-plasma passivation achieve better device performance, including the off-current below 0.1 pA//spl mu/m and the on/off current ratio higher than 10/sup 8/, and also better hot-carrier reliability than the H/sub 2/-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO/sub 2//poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH/sub 3/-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's.

Vacuum sealing of microcavities using metal evaporation

Abstract: A new encapsulation technique to seal a vacuum-tube microcavity hermetically at low pressures, based on aluminium evaporation, is presented and its performance is compared to conventional low-pressure chemical vapour deposition (LPCVD) reactive sealing. The microdiode consists of an in-cavity recessed single-crystalline silicon cathode tip above which a polycrystalline silicon anode is suspended on a silicon-rich nitride layer. The diode cavity is cleared from the sacrificial oxide in buffered HF through the horizontal etch-access channels between the polysilicon anode and the silicon-rich nitride isolation layer. Vacuum sealing of the cavity using LPCVD polycrystalline silicon results in polysilicon deposits ( > 50 nm) inside the cavity, and thus in a non-acceptable degradation of the cathode-tip curvature. When sealing is performed using aluminium evaporation, no deposits inside the cavity are observed and pressures below 10 Pa can be expected. Applications of the technique presented are not restricted to micro vacuum diodes, but also include various type of hermetically sealed micromechanical structures, where deposits inside the sealed cavity are undesirable.

Tungsten silicide deposition process

Abstract: A method of forming a gate metallization in a semiconductor integrated circuit by forming a polycrystalline silicon layer over a gate dielectric layer and then converting the polycrystalline silicon layer into tungsten or tungsten silicide by exposing the polycrystalline silicon to tungsten hexafluoride gas. The method enables the formation of polycrystalline silicon and tungsten or tungsten silicide in the same process cycle in the same reactor or in two similarly configured reactors or in two similarly configured clustered reactors.

Rapid Thermal Processing of Semiconductors

Abstract: Transient Heating of Semiconductors by Radiation. Recrystallization of Implanted Layers and Impurity Behavior in Silicon Crystals. Crystallization, Impurity Diffusion and Segregation in Polycrystalline Silicon. Component Evaporation, Defect Annealing and Impurity Diffusion in the III-V Semicondutors. Diffusion Synthesis of Silicides in Thin Film Metal-Silicon Structures. Rapid Thermal Oxidation and Nitridation. Rapid Thermal Chemical Vapor Deposition. Indexes.

Effect of grain size and dislocation density on the performance of thin film polycrystalline silicon solar cells

Abstract: Three kinds of important properties of the solar cell were calculated: short-circuit current density, open-circuit voltage, and conversion efficiency. Two equations which show the relationship between the minority-carrier diffusion length and the grain size or the etch pit density were used for the calculation. The dependence of the properties on the cell thickness were estimated as a function of grain size and etch-pit density. The effect of the internal reflectance with varying minority-carrier diffusion length was also examined. The results show that thin film polycrystalline silicon solar cells have the potential to attain an efficiency of 17% even at a film thickness of 2 μm if the grain size is bigger than 10 μm and the etch-pit density of less than 1×106 cm−2. The principal requirement is to achieve efficient light trapping.

Low Temperature Growth of Amorphous and Polycrystalline Silicon Films from a Modified Inductively Coupled Plasma

Abstract: A conventional inductive rf discharge is modified by inserting a discharge antenna in a plasma vessel with magnetic multipole confinement, which gives a high-density (~1011 cm-3) silane plasma at very low pressures (~1 mTorr). This new type of inductively coupled plasma (ICP) enables high-rate deposition (~1 nm/s) of a-Si:H films at low substrate temperatures of ~100°C, which have the photoconductivity of 10-5–10-4 S/cm and the dark conductivity of 10-10–10-9 S/cm. Moreover, microcrystalline or polycrystalline silicon films are formed on glass substrates at moderate temperatures of 200–300°C where the dark conductivity becomes comparable to the photoconductivity and the X-ray diffraction pattern shows sharp peaks corresponding to the silicon crystalline surfaces. Mass spectrometric measurements of the highly dissociated silane plasma show unique radical compositions; ~90% of ions are hydrogen species (H3+, H2+, H+) while the density of neutral radicals (SiH3, SiH2, SiH) is lower than that of ionic radicals (SiH3+, SiH2+, SiH+, Si+). Thus, the main precursor of film growth from high-density plasmas may be ionic radicals rather than neutral radicals.

Temperature dependent leakage currents in polycrystalline silicon thin film transistors

Abstract: We have studied the origins of the leakage current in polycrystalline silicon (poly-Si) thin film transistors. Temperature dependent transfer characteristics were measured as a function of drain voltage. Three kinds of leakage current were introduced to explain the experimental results. The leakage current may arise from the generation current at very low drain voltage, and may result in the same activation energy between leakage current and conductivity of undoped poly-Si. The leakage current may be due to the thermionic field emission via grain boundary defects in the intermediate drain voltage region. At high drain voltage and high negative gate voltage, the leakage current may result from the field enhanced tunneling of electrons in the valence band to the conduction band via grain boundary traps.

Specimen size effect on tensile strength of surface micromachined polycrystalline silicon thin films

Abstract: A new tensile tester using electrostatic force grip was developed to evaluate the tensile strength and the reliability of thin film materials. The tester was constructed in a SEM chamber for in-situ observation, and was applied for tensile testing of polycrystalline silicon (poly-Si) thin films with dimensions of 30-300 /spl mu/m long, 2-5 /spl mu/m wide and 2 /spl mu/m thick. It was found that the mean tensile strength is 2.0-2.7 GPa depending on the length of the specimens, irrespective of the specimen width. Statistical analysis of these size effects on the tensile strength predicted that the location of the fracture origin is on the edge of the specimen, which is identified by the SEM observation of the fracture surface of the thin films.

Microfabricated filter and capsule using a substrate sandwich

Abstract: A microfabricated filter made up of two bonded substrate structures, each consisting of single crystalline silicon can optionally be formed into a capsule. The pores of the filter consist of one or more channels disposed between the two substrate structures. The width of the channels are defined by a thickness of a sacrificial layer formed on one of the substrate structures. The filter includes pores having a precisely controlled pore width which may be as small as 5 nanometers. The filter provides a relatively high mechanical strength relative to filters having polycrystalline silicon structures and also has a high throughput and can be modified to have high resistance to adsorption of particles.

Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements

Abstract: The off-state current in n- and p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole–Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance acti...

Role of N2 addition on CF4/O2 remote plasma chemical dry etching of polycrystalline silicon

Abstract: The remote plasma chemical dry etching of polycrystalline silicon was investigated using various CF4/O2/N2 gas compositions The effects of O2 and N2 addition on the etch rate and surface chemistry were established Admixing O2 to CF4 increases the gas phase fluorine density and increases the etch rate by roughly sevenfold to a maximum at an O2/CF4 ratio of 015 The addition of small amounts of N2 (N2/CF4=005) can again double this etch rate maximum Strong changes in surface chemistry were also seen as a result of N2 addition to CF4/O2 Real-time ellipsometry and atomic force micro-roughness measurements reveal that nitrogen addition at low O2/CF4 ratios leads to the smoothing of surfaces, but to increased oxidation at high O2/CF4 ratios Based on etch rate data and gas phase species analysis, we propose that NO plays an important role in the overall etching reaction Variable tube lengths separated the reaction chamber from the discharge These tubes were lined with either quartz or Teflon liners In

Display device having a silicon substrate, a locos film formed on the substrate, a tensile stress film formed on the locos film, and TFTs formed on the tensile stress film

Abstract: A display device including a liquid crystal held between an active matrix substrate made up by arranging thin film transistors thereon, each using polycrystalline silicon as a semiconductor layer, in one-to-one relation to intersections between a plurality of signal lines and a plurality of scan lines, and an opposite substrate opposed to the active matrix substrate, wherein the active matrix substrate includes a film having tensile stress disposed at least below or above the semiconductor layer.

Characterization of electrothermal actuators and arrays fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process

Abstract: This paper presents the results of tests performed on a variety of electrothermal microactuators and arrays of these actuators recently fabricated in the four-level planarized polycrystalline silicon (polysilicon) SUMMiT process at the U.S. Department of Energy's Sandia National Laboratories. These results are intended to aid designers of thermally actuated mechanisms, and will apply to similar actuators made in other polysilicon MEMS processes. The measurements include force and deflection versus input power, maximum operating frequency, effects of long term operation, and ideal actuator and array geometries for different design criteria. A typical application in a stepper motor is shown to illustrate the utility of these actuators and arrays.

Substrate bias effects on low temperature polycrystalline silicon formation using electron cyclotron resonance SiH4/H2 plasma

Abstract: Polycrystalline silicon films were deposited at a substrate temperature of 300 °C by electron cyclotron resonance SiH4/H2 plasma-enhanced chemical vapor deposition. The effects of substrate dc bias during deposition on the crystallinity and the surface roughness of the deposited films were investigated in the range from −150 to +50 V by using x-ray diffraction, scanning electron microscopy, and atomic force microscopy. It was found that the positive biases applied to the substrate improved the crystallinity and the surface roughness. To clarify the substrate dc bias effects on the crystallinity and the surface roughness, the sheath potential, ion current, and temperature on the substrate surface were measured. It is determined that improvement of the crystallinity and the surface roughness is due to the decrease of ion flux to the substrate when positive bias is applied to the substrate.

Negative differential resistance device based on tunneling through microclusters, and method therefor

Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N + . The amorphous silicon is simultaneously crystallized and oxidized in a dry N 2 and O 2 mixture. The result is a layer of amorphous SiO 2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO 2 . A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Purely Intrinsic Poly-silicon Films for n-i-p Solar Cells

Abstract: Polycrystalline silicon films have been prepared by hot wire chemical vapor deposition (HWCVD) at a relatively low substrate temperature of 430° C at a high growth rate (>5 A/s) by optimizing the hydrogen dilution of the silane feedstock gas, the gas pressure and the wire temperature. The optimized material has 95% crystalline volume fraction with complete coalescence of grains. The grains with an average size of 70 nm have a preferential orientation along the (220) direction. Large structures up to 0.5 µ m could be observed by atomic force microscopy (AFM). An activation energy of 0.54 eV for the electrical transport and a low carrier concentration (<1011 cm-3) confirmed the intrinsic nature of the films. A white light photoconductivity of 1.9×10-5 Ω-1 cm-1, a high minority carrier diffusion length of 334 nm and a low (<1017 cm-3) defect density ensure that the poly-Si:H films possess device quality. A very small temperature dependence of the Hall mobility (0.012 eV) indicates negligible barrier to carrier transport at the grain boundaries. A single junction n-i-p cell incorporating HWCVD poly-Si:H in the configuration n+-c-Si/i-poly-Si:H/p-µc-Si:H/ITO yielded 3.15% efficiency under 100 mW/cm2 AM1.5 illumination and a current density of 18.2 mA/cm2 was achieved for only 1.5 µ m thick i-layer.

Release of metal impurities from structural defects in polycrystalline silicon

Abstract: Metal impurity release from structural defects in polycrystalline silicon was studied following thermal treatments, and, in addition, a correlation between impurity distributions and structural defects was established. Impurities were mapped with synchrotron-based x-ray fluorescence in the as-grown state, after rapid thermal annealing and following aluminum gettering treatments. The goal of this work was to determine if impurity release from structural defects limits gettering of metal impurities. The results reveal that nickel and copper metal impurities are primarily found at dislocations in as-grown crystals, and the release of these impurities from defects occurs rapidly with no apparent barrier to dissolution. Gettering treatments dissolved metal impurity precipitates to <2–5 nm in radii; however, the material performance was not greatly enhanced.

Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

Buffered substrate for semiconductor devices

Abstract: The invention provides a buffered substrate that includes a substrate, a buffer layer and a silicon layer. The buffer layer is disposed between the substrate and the silicon layer. The buffer layer has a melting point higher than a melting point of the substrate. A polycrystalline silicon layer is formed by crystallizing the silicon layer using a laser beam.

Fabrication process of semiconductor device

Abstract: After forming an isolation layer and a well region on and in a silicon substrate, a gate oxide layer, a gate electrode of polycrystalline silicon and an oxide layer on the gate electrode are formed. Subsequently, a side wall of a nitride layer is formed. Then, the oxide layer on the gate electrode is removed. Next, selective growth of impurity doped silicon is performed at a temperature lower than or equal to 800° C. to form an elevated source-drain region in a source-drain region. Also, a polycrystalline silicon layer is formed on the gate electrode. Thereafter, by performing heat treatment, the impurity is diffused from the source-drain region to the surface of the silicon substrate to form a source-drain diffusion layer. Simultaneously, conductivity is provided to the entire gate electrode by diffusing impurity from the polycrystalline silicon layer to the gate electrode.