Showing papers on "Power integrity published in 2006"
TL;DR: In this article, the authors proposed a closed-form expression for the parasitics associated with the interconnects of the decoupling capacitors of a dc power distribution network.
Abstract: Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it Full-wave methods are often employed to study the power integrity problem While full-wave methods can be accurate, they are time and memory consuming The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived This allows both frequency and transient responses to be done with SPICE simulation
113 citations
TL;DR: In this paper, a photonic crystal power/ground layer (PCPL) is proposed to suppress the power and ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits.
Abstract: A novel photonic crystal power/ground layer (PCPL) is proposed to efficiently suppress the power/ground bounce noise (P/GBN) or simultaneously switching noise (SSN) in high-speed digital circuits. The PCPL is designed by periodically embedding high dielectric-constant rods into the substrate between the power and ground planes with a small area filling ratio less than 10%. The PCPL can efficiently eliminate the SSN (over 60 dB) with broad stopband bandwidth (totally over 4 GHz) below the 10-GHz range, and in the time domain, the P/GBN can be significantly reduced over 90%. The PCPL not only performs good power integrity, but also keeps good signal quality with significant improvement on eye patterns for high-speed signals with via transitions. In addition, the proposed designs perform low radiation (or electromagnetic interference) caused by the SSN within the stopbands. These extinctive behaviors both in signal integrity and electromagnetic compatibility are demonstrated numerically and experimentally. Good agreements are seen. The bandgap maps to help design the PCPL structure are also demonstrated based on the two-dimensional finite-difference time-domain method
43 citations
05 Nov 2006
TL;DR: In this paper, the transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density.
Abstract: The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steady-state thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven via-stapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. The via reduction would be higher for the 3D design with more device layers
40 citations
24 Jul 2006
TL;DR: A triangularization based structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid and achieves up to 133times and 109times speedup in macromodel building and simulation respectively.
Abstract: In this paper, a triangularization based structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is represented by interconnected basic blocks according to current density, and basic blocks are further clustered into compact blocks, each with a unique pole distribution. Then, the system is transformed into a triangular system, where compact blocks are in its diagonal and the system poles are determined only by the diagonal blocks. Finally, projection matrices are constructed and applied for compact blocks separately. The resulting macromodel has more matched poles and is more accurate than the one using flat projection. It is also sparse and enables a two-level analysis for simulation time reduction. Compared to existing approaches, TBS in experiments achieves up to 133/spl times/ and 109/spl times/ speedup in macromodel building and simulation respectively, and reduces waveform error by 33/spl times/.
27 citations
09 Apr 2006
TL;DR: The design methodology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence, and integrates the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology.
Abstract: As technology advances, the metal width decreases while the global wire length increases This trend makes the resistance of the power wire increase substantially Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasible to co-synthesize P/G network with floorplan To make the co-synthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method In this paper, we present a method for floorplan and P/G network co-synthesis based on an efficient P/G network analysis scheme and the B*-tree floorplan representation We integrate the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence
25 citations
TL;DR: In this article, the authors present a review of the electrical characterization and modeling of IC packages and interconnects, focusing mainly on high-frequency signal related characterization and power integrity issues.
Abstract: This paper reviews current approaches to the electrical characterization and modeling of IC packages and interconnects. An overview of both frequency and time-domain measurement methods and summaries of equivalent circuit model selection and extraction methodologies are included. Additionally, an overview of numerical methods for electromagnetic modeling is included for completeness. Finally, relevant case studies from the literature are summarized to further supplement the discussed techniques. The focus is primarily on high-frequency signal related characterization and power integrity issues are not directly considered in this paper. This paper is presented in the context of the growing requirement for package and interconnection electrical models for high-speed and miniaturized systems.
24 citations
15 May 2006
TL;DR: In this article, the power integrity of the system chip plus chip package determines the RF emission potential and is thus a key quality parameter of complex integrated circuits like microcontrollers for automotive applications.
Abstract: The power integrity of the system chip plus chip package determines the RF emission potential and is thus a key quality parameter of complex integrated circuits like microcontrollers for automotive applications. However, modeling and simulation of power integrity and thus electromagnetic emission must be applied as early as possible in the IC design process. This paper presents two approaches: (1) the case study simulation in a very early IC design phase and (2) the accurate netlist/layout-based simulation at a later design phase. Both implementations have been used in combination with the Infineon 32-bit microcontroller TC1796.
21 citations
24 Jan 2006
TL;DR: This paper proposes a parallel-distributed time-domain circuit simulation algorithm based on LIM, and an effective modeling of frequency-dependencies of the PDNs, such as skin effects and dielectric losses, to solve by LIM.
Abstract: In this paper, we focus on the verification of the PCB/package power integrity, which becomes very important for the design of state-of-art high speed digital circuits. The simulation of power distribution networks (PDNs) of the PCB/package, which can be modeled as a large number of RLC lumped components, is a time-consuming task for using the conventional circuit simulator, such as SPICE. For this problem, we propose a parallel-distributed time-domain circuit simulation algorithm based on LIM. Furthermore, an effective modeling of frequency-dependencies of the PDNs, such as skin effects and dielectric losses, to solve by LIM is proposed.
14 citations
27 Mar 2006
TL;DR: Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening of signal-integrity and power-Integrity in a case where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts.
Abstract: Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters.
14 citations
09 Apr 2006
TL;DR: This paper shows that using impedance as constraints leads to large overdesign and then develops a noise driven optimization algorithm for decoupling capacitors in packages for power integrity that reduces the decoupled capacitor cost by 3x and is also more than 10x faster even with explicit noise computation.
Abstract: The existing decoupling capacitance optimization approaches meet constraints on input impedance for package. In this paper, we show that using impedance as constraints leads to large overdesign and then develop a noise driven optimization algorithm for decoupling capacitors in packages for power integrity. Our algorithm uses the simulated annealing algorithm to minimize the total cost of decoupling capacitors under the constraints of a worst case noise. The key enabler for efficient optimization is an incremental worst-case noise computation based on FFT over incremental impedance matrix evaluation. Compared to the existing impedance based approaches, our algorithm reduces the decoupling capacitor cost by 3x and is also more than 10x faster even with explicit noise computation.
13 citations
24 Jul 2006
TL;DR: This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems and some results based on the application of this methodology on test systems are presented.
Abstract: This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems. The paper briefly outlines some new modeling and simulation techniques that have been developed to enable the proposed methodology. Some results based on the application of this methodology on test systems are also presented.
TL;DR: In this article, an electromagnetic crystal power substrate (ECPS) was proposed for suppressing the power/ground planes noise (P/GPN) and the corresponding electromagnetic interference (EMI).
Abstract: An electromagnetic crystal power substrate (ECPS) in a high-speed circuit package is proposed for suppressing the power/ground planes noise (P/GPN) and the corresponding electromagnetic interference (EMI). The ECPS is simply realized by periodically embedding the high dielectric-constant rods into the conventional package substrate between the continuous power and ground planes. With a small number of embedded rods and low rod filling ratio, the proposed ECPS design can efficiently eliminate the noise of 30dB in average within several designed stopbands. In addition, the radiation or EMI resulting from the P/GPN is also significantly reduced over 25dB in the stopbands. The excellent noise and EMI suppression performance for the proposed structure are verified both experimentally and numerically. Reasonably good consistency is seen
IBM1
TL;DR: The proposed method utilizing piece-wise modeling approach to dissect the package structures into component models and unify them into a single simulation circuit can be extended to full system simulation, resulting in fast computation for design space exploration where massive simulations are necessary.
Abstract: As bit rates are approaching 10 Gbps with ever-increasing requirement for package performance, multi-layer FC-BGA package are gradually becoming a de facto for high performance system. Since the signal frequency is now in the range of noise generated by power plane resonances, it presents a major challenge to model the complex interaction between signal traces and power/ground planes. Any attempt to segment the package into smaller pieces to simplify the computation may compromise the accuracy, diminishing the resonance effect. Conversely, full package model created from field solver is impractical and too expensive to generate. This paper presents a methodology to unify signal and power integrity into a single simulation model derived from conventional signal and power integrity models. The proposed method utilizes piece-wise modeling approach to dissect the package structures into component models and unify them into a single simulation circuit. The proposed approach can be extended to full system simulation, resulting in fast computation for design space exploration where massive simulations are necessary
Journal Article•
TL;DR: In this paper, the authors developed an LSI noise model and simulation methodology to analyze power integrity inside system-on-a-chip (SoCs) and applied it in product development.
Abstract: Semiconductor scaling is making power integrity inside system-on-a-chips (SoCs) a major design issue. To investigate this issue, we developed an LSI noise model and simulation methodology to analyze power integrity. Using this methodology, we can simulate power supply noise inside an LSI, for example, the simultaneous switching noise of I/O circuits and core noise caused by dynamic switching currents. We can also use this model in the initial design stage to optimize the power wiring and minimize the power pin-count and thereby minimize the chip cost. In this paper, we first describe the noise that must be considered when designing an LSI’s power system. We then describe the structure and generation flow of the LSI noise model, the measurement results of a test chip we used for verifying the model’s accuracy, and the application of the model in product development.
09 May 2006
TL;DR: In this article, the authors highlight the combined effort of signal integrity and power delivery simulations which are performed to obtain the optimal topology, terminations and decoupling solution for motherboard implementation of 533MT/s DDR2 devices that are soldered directly on the motherboard.
Abstract: Increased frequencies and reduced rise times have made signal integrity simulations an integral part of high speed board designs. Signal integrity simulations are usually performed considering an ideal power source and power integrity simulations are performed assuming ideal transmission lines. But due to ever decreasing rise times errors creep into signal quality and timing analysis by ignoring the effects of the PDN. This paper outlines the necessity and the impact of including power delivery network effects for Signal quality and timing analysis. This paper highlights the combined effort of Signal integrity and power delivery simulations which are performed to obtain the optimal topology, terminations and decoupling solution for motherboard implementation of 533MT/s DDR2 devices that are soldered directly on the motherboard.
01 Sep 2006
TL;DR: In this article, a case study for a typical rectangular power-ground structure was conducted for low-impedance power distribution network design to ensure power integrity as well as signal integrity for high speed packages and printed circuit boards.
Abstract: Design of low-impedance power distribution network is vital to ensure power integrity as well as signal integrity for high-speed packages and printed circuit boards (PCBs). In this paper, we conducted a case study for a typical rectangular power-ground structure. Both analytical and numerical methodologies are used for this purpose. We studied how the impedance of a power-ground structure is affected by the location of the noise injection point, lossy substrate, edge radiation, decoupling capacitors and vias. Conclusions are drawn for this study.
03 Jan 2006
TL;DR: A comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics, including Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered.
Abstract: Summary form only for tutorial. Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics. Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Foundations for statistical parasitic extraction and results from correlation to silicon are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered.
09 Oct 2006
TL;DR: In this article, a CPU core-power interconnect design was pre-viously proposed for reducing radiated emissions that result from current injected into a motherboard, where the EMI-suppressing design increases the inductance to the motherboard to filter the harmonics of the processor.
Abstract: A CPU core-power interconnect design was pre- viously proposed for reducing radiated emissions that result from current injected into a motherboard. The EMI-suppressing design increases the inductance to the motherboard to filter the harmonics of the processor. The change in inductance and resistance, however, may prove detrimental to the core power integrity. Higher inductance will shift the chip-package resonance, possibly rendering the package capacitors useless. A significant resistance increase could incapacitate the VRM, cause excessive voltage fluctuations across the die, as well as decrease the efficiency of the circuit. The change in inductance and resistance is analyzed, and the effect on power integrity is discussed herein.
05 Jul 2006
TL;DR: In this paper, the Cell Reference Board was evaluated in terms of signal integrity, power integrity and EMI for a multi-GHz differential channel bus on a board with high voltage opening and low timing jitter.
Abstract: Higher bandwidth is required to handle a larger volume of information for the high-definition video application in the near future. A multi-GHz differential channel bus on a board must be carefully designed to maintain good eye-diagram with high voltage opening and low timing jitter. Crosstalk noise among differential buses, reflection at the receiver noise, and via discontinuities must be taken into consideration by modeling the interconnections prior to design and fabrication. After being fabricated and assembled, the Cell Reference Board was evaluated in terms of signal integrity, power integrity and EMI.
01 Oct 2006
TL;DR: NiP used for NoC is designed and analyzed regarding of signal integrity and power integrity and the measured results of the NiP show perfect communications between NoCs.
Abstract: SiP (system-in-package) and SoC (system-on-chip) are familiar to us. In this paper, we firstly define advanced concepts of NoC (network-on-chip) and NiP (network-in-package). Design and implementation of NoC are explained and then, NiP used for NoC is designed and analyzed regarding of signal integrity and power integrity. The low-power packet-switched NoC with hierarchical star topology is designed and implemented for high-performance SoC platform. An NiP integrating four NoCs is fabricated in a 676-BGA-type package for large and scalable systems and the measured results of the NiP show perfect communications between NoCs
09 May 2006
TL;DR: In this article, the authors proposed two simple procedures to model the simultaneous switching noise (SSN) and evaluate its effects in any point of the board, so as to evaluate the effects of the SSN on the performance of the integrated circuits.
Abstract: When the performances of the electronic technology increase (higher frequencies, more power, lover power supply, faster transistors, reduced chip dimensions), designing electronic equipment becomes more challenging for the electronic engineers. Signal and power integrity on board become of paramount importance. One of the main causes of board malfunctions and electromagnetic radiation is the simultaneous switching noise (SSN) due to the integrated circuits soldered on the board. The paper proposes two simple procedures to model the SSN, so to evaluate its effects in any point of the board
01 Sep 2006
TL;DR: This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology, and proves that gate delay depends on average voltage drop.
Abstract: Power integrity is an crucial design issue in nano-meter technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop.
TL;DR: In this paper, a new simulation method for the full chip-level signal and powerintegrity analysis is developed, where CAD layout data is converted into SPICE transmission line models considering silicon substrate effects.
Abstract: With an increase in operating frequency and the complexity of system on a chip (SOC), it becomes important to consider the noise generated along the signal and power/ground interconnections that leads to malfunction. We have developed a new simulation method for the full chip-level signal and power-integrity analysis. The CAD layout data is converted into SPICE transmission line models considering silicon substrate effects. To remove the limitation of size and complexity of layout data in the real LSI chips, a sectioning method using MOR with super linear solver has been introduced. The proposed method can also be extended to the computation of current/voltage distributions leading to EMI analysis
01 Jan 2006
TL;DR: The generalized method of the time-domain circuit simulation based on LIM, applicable to any structure of circuits by combination with the SPICE-like method, is shown.
Abstract: In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.
24 Jan 2006
TL;DR: This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multiprocessor integrating quadruple cores and proposes a power integrity analysis and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board.
Abstract: This paper introduces a 512Gops, 10GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis Our multi-processor is designed to decode MP@HL streams without any dedicated circuits To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os However, this makes for a high level of power supply noise We then applied an interface timing margin analysis tool that took power supply noise into account, and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board As a result, we succeeded in operating the processor at 533MHz with the 2ch 64bit main memory IF at 266MHz and 64bit system bus at 178MHz
09 Oct 2006
TL;DR: This paper compares two compact 2D FDFD methods using four and six components of electromagnetic fields, which are applied to analyzing transmission lines with open boundaries, and applies them to extraction of circuit parameters for signal integrity analysis of high-speed circuit systems.
Abstract: Compact 2D FDFD (two-dimensional finite- difference frequency-domain) methods were initially proposed by other researchers to solve the propagation constant of shielded uniform guided wave structures. In this paper, firstly we compare two compact 2D FDFD methods using four and six components of electromagnetic fields, which are applied to analyzing transmission lines with open boundaries. Then we extend them to extract the frequency-dependent circuit parameters of transmission lines. These R, L, C, G circuit parameters extracted via 1D transmission line theory are readily to be used for signal integrity analysis of high-speed circuits. I. INTRODUCTION High-speed effects of interconnect structures due to the increase in operating speed and decrease of the feature size in modern VLSI circuits, have to be carefully accounted for accurate signal integrity, power integrity and EMI/EMC analysis of modern circuit systems. The use of transmission line model becomes necessary in order to accurately capture the high-speed effects of interconnects. For the purpose of creating a proper transmission line model, very often the equivalent circuit parameters (R, L, C and G) need to be known in advance (1). This paper will focus on the compact 2D FDFD methods and apply them to extraction of circuit parameters. Characterization of transmission lines has been a topic of interest for many years, especially the analysis of the basic microstrip-like transmission line. Recently the compact two dimensional finite-difference frequency domain (2D FDFD) methods have been studied by several researchers (2-5) to analyze guided wave structures. Apart from its simple formulation, the advantage of 2D FDFD method is that we can obtain all the modes and modal field distribution of a uniform guided wave structure by solving an eigenvalue problem. The compact 2D FDFD method using four (3) and six (2, 5) field components have been proposed. In this paper, we will compare these two compact 2D FDFD methods used for analysis of guided wave structures. Then we will apply them to extract circuit parameters for the purpose of signal integrity analysis of high-speed circuit systems.
01 Oct 2006
TL;DR: In this paper, the authors investigated two main new ways to reduce the resonant impedance, which are using magnetic substance or graphite as plane conductor material and adopting insulator material with high permittivity and loss tangent.
Abstract: The power bus structure in PCB or IC, which is consisting of two parallel planes separated by an insulator, behaves as a cavity resonator. The high resonant impedance at certain resonant frequency between the IC or PCB's power and ground layers is the cause of some signal integrity problems. Based on the theory of parallel planes cavity resonator, this paper deducts the relation functions between the resonant impedance, resonant frequency, resonant quality factor and the electromagnetic parameters of power/ground planes structure. By using the deductions above, this paper investigated 2 main new ways to reduce the resonant impedance, which are using magnetic substance or graphite as plane conductor material and adopting insulator material with high permittivity and loss tangent. And the effects of the two ways above in resonant impedance damping are expressed clearly by the simulation results.