Showing papers on "Programmable logic array published in 2009"

Memristor―CMOS Hybrid Integrated Circuits for Reconfigurable Logic

Abstract: Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

Abstract: An automated method and apparatus for positioning gate array circuits in an integrated circuit design An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits

Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Test and bring-up of an enhanced cascade interconnect memory system

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Abstract: A diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process without additional process is presented. The requirements of various components in the anti-fuse cell are discussed. The solution to high voltage reliability problem when programming the gate oxide anti-fuse is provided. Measurement results are performed to confirm the functionality of the design.

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Abstract: Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.

Digital Design Using Field Programmable Gate Arrays

Abstract: 1. Introduction. 2. Design Specifications. 3. Design Methodologies. 4. Design Verification and Testing. 5. Combinational Logic Design. 6. Finite State Machine Design. 7. Timing Issues. 8. Datapath Design. 9. Case Studies. 10. Impact of FPGA. Appendix A: Vendors. Appendix B: Data Sheets. Appendix C: CAD Tools. Reference. Index.

SAD-Based Stereo Matching Using FPGAs

Abstract: In this chapter we present a field-programmable gate array (FPGA) based stereo matching architecture. This architecture uses the sum of absolute differences (SAD) algorithm and is targeted at automotive and robotics applications. The disparity maps are calculated using 450×375 input images and a disparity range of up to 150 pixels. We discuss two different implementation approaches for the SAD and analyze their resource usage. Furthermore, block sizes ranging from 3×3 up to 11×11 and their impact on the consumed logic elements as well as on the disparity map quality are discussed. The stereo matching architecture enables a frame rate of up to 600 fps by calculating the data in a highly parallel and pipelined fashion. This way, a software solution optimized by using Intel’s Open Source Computer Vision Library running on an Intel Pentium 4 with 3 GHz clock frequency is outperformed by a factor of 400.

Inversion schemes for sublithographic programmable logic arrays

Abstract: A programmable logic array (PLA) needs its inputs available in both the positive and negative polarities. In lithographic-scale VLSI PLAs, programmable array logics (PALs) and programmable logic devices (PLDs) a buffer and inverter at the PLA input typically produces both polarities from a single polarity input. However, the extreme regularity required for sublithographic designs has driven nanoscale architectures to consider alternate solutions. Consequently, the authors compare three schemes: one based on producing both polarities in a restoration stage (selective inversion), one based on a local inversion stage and one based on a full dual-rail logic implementation. The authors develop a mapping flow for the dual-rail logic and quantify its cost in both logical product terms and physical implementation area and also develop area and timing models for all three schemes. Mapping benchmarks from the Toronto 20 set, the authors are able to show that the local inversion scheme is faster (less than one-fifth the latency), lower energy (one-half the energy) and comparable size to the selective inversion scheme and faster (less than half the latency), smaller (one-third of the area) and lower energy (one-ninth the energy) than the dual-rail scheme.

Reconfiguration of an accelerator module having a programmable logic device

Abstract: Reconfiguration of an accelerator module having a programmable logic device is described, where the reconfiguration is performed during runtime without rebooting. For example, a computer is put into a sleep mode, the computer having the accelerator module installed therein. A programmable logic device of the accelerator module is reconfigured while the computer is in the sleep mode.

Scaling prospect of optically differential reconfigurable gate array VLSIs

Abstract: Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 μm and 0.35 μm CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability

Abstract: Programmable logic arrays (PLAs) using self-assembly nanowire crossbars have shown promising potential for future nano-scale circuit design However, due to the density and size factors of nanowires and molecular switches, the fabrication fault densities are much higher than those of the conventional silicon technology, and hence pose greater design challenges In this paper, we propose a novel defect-aware logic mapping framework via Boolean satisfiability (SAT) Compared with the prior works, our technique considers PLA defects on both input and output planes at the same time This synergistic approach can help solve logic mapping problems with higher defect rates The proposed method is universally suitable for various nano-scale PLAs, including AND/OR, NOR/NOR structures, etc The experimental results have shown that it can efficiently solve large mapping problems at a total defect rate of 20% or even higher We further investigate the impact of different defects on PLA mapping, which helps set up an initial contribution for yield estimation and utilization of partially-defective PLAs

SOA-Based Ultrafast Multifunctional All-Optical Logic Gates With PolSK Modulated Signals

Abstract: In this paper, we propose a novel scheme for ultrafast multifunctional all-optical logic gates, which can achieve not only simple logic gates including AND, NOR, Smacr 1Smacr2,Smacr1Smacr2,XNOR, and XOR but also complex logic gates including half adder, half subtracter, decoder, and comparer based on four-wave mixing in semiconductor optical amplifiers (SOAs) with polarization-shift-keying (PolSK) modulated signals. A comprehensive polarization-dependent broadband dynamic model of this kind of ultrafast multifunctional all-optical logic gates is presented. By numerical simulation, the multifunctional all-optical logic gates are theoretically realized at 40 Gbit/s. The effects of two input signal powers, injected current, frequency detuning, and polarization dependence of SOA on the output performance of the multifunctional all-optical logic gates are theoretically investigated in detail. The results indicate that this scheme is free of pattern effect due to using the PolSK modulation format. Moreover, the nice eye opening of the logic gates indicates the good performance of the proposed ultrafast multifunctional all-optical logic gates. This scheme is potential for applications in future high bit rate optical networks.

Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)

Abstract: After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noiseimmune threshold logic(SPD-NTL). It is based on combining the split-level precharge differential logic, with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic. Another idea included in the design of the SPD-NTL gates is the use of two threshold logic banks implementing fand f_bar, and working together with the noise suppression logicblocks for enhanced performances. Simulations in 0.25 im CMOS @ 2.5 V show the functionality of the gate up to 2 GHz. An advanced layout based on high matching centroid techniques is currently under development.

Designing fault tolerant FSM by nano-PLA

Abstract: The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.

Complete Logic Functionality of Reconfigurable RTD Circuit Elements

Abstract: Innovative nanoscale devices have been developed to enhance future circuit design to overcome physical barriers hindering the CMOS technology. Among the emerging nanodevices, resonant tunneling diodes (RTDs) have demonstrated promising electronic features due to their high-speed switching capability and functional versatility. Great circuit functionality can be achieved through integrating heterostructure FETs (HFETs) in conjunction with RTDs to modulate effective negative differential resistance. In this paper, we propose novel programmable logic elements (PLEs) implemented in threshold gates (TGs) and multithreshold TGs by exploring RTD/HFET monostable-bistable transition logic element (MOBILE) principles. Our three-input PLE can be configured through five binary control bits to realize all the three-variable logic functions, which is, to the best of our knowledge, the first single RTD-based structure that provides complete Boolean logic implementation. It is also a more efficient reconfigurable circuit element than a general lookup table that requires eight configuration bits for three-variable functions. We further extend the design concept to construct a more versatile four-input PLE. A comprehensive comparison of three- and four-input PLEs provides an insightful view of design tradeoffs between performance and area. We present the mathematical proof of PLE's logic completeness based on Shannon expansion, as well as the HSPICE simulation results of the programmable and primitive RTD/HFET gates that we have designed. An efficient control bit generating algorithm is developed by using a special encoding scheme to implement any given logic function. Based on our PLE structures, we propose a reconfigurable architecture, namely MORE, which offers dynamic reconfigurability without incurring latency overheads, due to the intrinsic self-latching property of MOBILE circuits. An efficient reconfiguration data generation algorithm is also built to take full advantage of our MORE architecture. The experimental results indicate that it can help reduce the reconfiguration cost by 37% on average.

Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources

Abstract: A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Harnessing Human Computation Cycles for the FPGA Placement Problem.

Abstract: Harnessing human computation is an approach to find problem solutions. In this paper, we investigate harnessing this human computation for a Field Programmable Gate Array (FPGA) placement problem. We create a game called Plummings. In this game, a player attempts to reduce the critical path of a digital design mapped to an FPGA by swapping clusters on the array, but the problem details are abstracted away, and instead, the game simply presents a challenging problem where paths must be minimised to save the game characters the Plummings. Once players have played a level, the placement is can be evaluated in VPR. Our results show that 4 human players over a set of 5 benchmarks can create placement solutions with comparable critical paths compared to VPR’s solutions. This is not always the case, and we suggest some reasons and further approaches to improving our results.

Developed Method of FPGA-based Fuzzy Logic Controller Design with the Aid of Conventional PID Algorithm

Abstract: This paper proposes developed method to design a digital fuzzy logic controller with the aid of conventional Proportional - integral - derivative (PID) controller using field programmable gate array (FPGA). The method used to design a PID Fuzzy Logic controller is to design it as Proportional - derivative Fuzzy Logic controller (PDFLC) and Proportional -integral fuzzy logic controller (PIFLC) connected in parallel through a summer. This method reduces the number of rules needed significantly. To simplify the controller design, we designed the PIFLC by accumulating the output of PDFLC. The contribution in this method are, firstly, to reduce the huge number of fuzzy rules required in the normal design for PIDFLC from 512 rules (in the case of three inputs PIDFLC) to 64 rules (in the case of two inputs PIDFLC). Secondly, to avoid the difficulties to formulate the control rules with the input variable sum-of-error e in the case of PIFLC input as its steady-state value is unknown for most control problems. This method also enables us to design the controller to work as PDFLC, PIFLC or PIDFLC depending on two (one-bit) external signals with programmable fuzzy sets and programmable rule table using VHDL language for implementation on FPGA device, and to employ the new technique of fuzzy algorithm in order to serve a wide range of the physical systems which require a real-time operation. From the compilation and timing simulation results, the controller is able to produce a fast response in 20.8 ns with 75.85 MHz of frequency. The time required between validin for the first cycle is 4.423 ns. From analysis and synthesis summary, we got that the design contain of 127 total pins and 215 combinational functions and 215 logic elements. From these specifications and with compare it with other design using software; the controller has the ability to serve a wide range of the physical systems which require a real-time operation.

FPGA-based Implementation of Digital Logic Design using Altera DE2 Board

Abstract: In control applications, most of the physical systems require a real-time operation to interface high speed constraints; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This paper presents an Experimental implementation of digital logic designs on the Altera DE2 board which presented as an educational and development board, in order to check the flexible implementation with FPGA and to get the better and safely ways to use these specifications during any design implementations. The implementation in this paper contains of two types of digital logic design, the first one is Digital UP-counter design which designed using Verilog language, the experimental results for this design displayed on the 7-segment with the sequence of HEX0 and HEX1. The second design is the proportional-derivative (PD) fuzzy logic controller which contain of three parts, Fuzzifier, inference engine and Defuzzifier. The PD Fuzzy logic controller was designed using VHDL language. Groups of two membership function with 5 linguistics variable and rule table of 25 rules were used to generate the control surface of the PD fuzzy logic controller, and to generate the simulation before the implementation, these groups are stored in the memory blocks, this block is generated using MegaWizard Plug-in Manager provided by Altera Quartus II program, the design using MegaWizard is important to ensure the good design specifications, the surfaces with these groups compared with the same design using MATLAB. By subtracting both type of surfaces, a results have been obtained, these results proved that the FPGA-based fuzzy controller is very close to the software- based controller using MATLAB.

Method for implementing functional changes into a design layout of an integrated device, in particular a system-on-chip, by means of mask programmable filling cells

Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.

All-optical linear reconfigurable logic with nonlinear phase erasure.

Abstract: We introduce a novel all-optical logic architecture whereby the gates may be readily reconfigured to reprogram their logic to implement (N)AND/(N)OR/X(N)OR. A single gate structure may be used throughout the logic circuit to implement multiple truth tables. The reconfiguration is effected by an optical reference signal. The reference may also be adapted to an arbitrary Boolean complex alphabet at the gate logic inputs and calibrated to correct gate imperfections. The all-optical gate structure is partitioned into a linear interferometric front end and a nonlinear back end. In the linear section, two optical logic inputs, along with a reference signal, linearly interfere. The nonlinear back end realizes a phase-erasure (or phase-reset) function. The reconfiguration and recalibration capabilities, along with the functional decoupling between the linear and nonlinear sections of each gate, facilitate the potential aggregation of large gate counts into logic arrays. A fundamental lower bound for the expended energy per gate is derived as 3hν+kT ln2 Joules per bit.

Phase-Change-Driven Programmable Switch for Nonvolatile Logic Applications

Abstract: A new device concept for a programmable switch employing a phase-change memory element was proposed, in which a unique four-terminal structure having two operating channels was so designed as to effectively separate two functions of programming and pass-gating. The proposed device was successfully fabricated, and its operational behaviors were demonstrated.

A Battery-Free Tag for Wireless Monitoring of Heart Sounds

Abstract: We have developed a wearable, battery-free tag that monitors heart sounds. The tag powers up by harvesting ambient RF energy, and contains a low-power integrated circuit, an antenna and up to four microphones. The chip, which consumes only 1.0uW of power, generates digital events when the outputs of any of the microphones exceeds a programmable threshold voltage, combines such events together by using a programmable logic array, and transmits them to a base station by using backscatter modulation. The chip can also be programmed to trade-off microphone sensitivity for power consumption. In this paper, we demonstrate that the tag, when attached to the chest, can reliably measure heart rate at distances up to 7m from an FCC-compliant RF power source. We also suggest how delays between signals measured by microphones at the wrist and neck can be used to provide information about relative blood-pressure variations.

Evolution of Programmable Logic

Abstract: The chapter discussed contemporary field-programmable logic devices and their evolution, starting from the simplest programmable logic devices such as PROM, PLA, PAL and GAL, and finishing with very sophisticated chips such as CPLD and FPGA. This analysis shows particular features of different logic elements and permits to optimize the FSM logic circuits, in which some particular elements are used. The analysis is accompanied by some examples for systems of Boolean functions implementation using PROM, PLA and PAL chips. The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter.

Defects and faults in QCA-based PLAs

Abstract: Defect tolerance will be critical in any system with nanoscale feature sizes. This article examines some fundamental aspects of defect tolerance for a reconfigurable system based on Quantum-dot Cellular Automata (QCA). We analyze a novel, QCA-based, Programmable Logic Array (PLA) structure, develop an implementation independent fault model, and discuss how expected defects and faults might affect yield. Within this context, we introduce techniques for mapping Boolean logic functions to a defective QCA-based PLA. Simulation results show that our new mapping techniques can achieve higher yields than existing techniques.

Dynamic reconfiguration in a PSoC device

Abstract: Cypress PSoC (Programmable System on Chip) is a device that consists of programmable analog blocks, programmable digital blocks and an MCU. PSoC has become increasingly popular in embedded systems due to its programmable analog and dynamic reconfigurable capabilities.

Efficient realisation of MOS-NDR threshold logic gates

Abstract: A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.

Automated Pin Multiplexing for Programmable Logic Device Implementation of Integrated Circuit Design

Abstract: In an embodiment, a method to automatically select groups of signals to be multiplexed on pins of a programmable logic device in a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The set of signals that may be candidates for multiplexing may be received (e.g., the set may be output by programmable logic device design tool). Clock domain tracing may be performed, and signals that have matching clock domains may be identified as candidates for multiplexing. Signals from matching clock domains may be grouped (up to a maximum number of signals that may be multiplexed on one pin) and assigned to pins of the programmable logic devices.