Showing papers on "Semiconductor device published in 1994"

Dual-function semiconducting polymer devices : light-emitting and photodetecting diodes

Abstract: Thin film devices made with poly[2‐methoxy‐5‐(2’‐ethyl‐hexyloxy)‐1,4‐phenylene vinylene], MEH‐PPV, are known to be efficient light‐emitting diodes. The same devices, under reverse bias, exhibit excellent sensitivity as photodiodes. Thus the polymer tunnel diode is a dual‐function device. For the Ca/MEH‐PPV/ITO (indium/tin oxide) layered structure, the external quantum efficiency for electroluminescence is ≊1% photons/electron (forward bias ≳2.5 V). The same device is sensitive as a photodiode: The dc sensitivity (−10 V, reverse bias) is 9×10−2 A/W (at ∼1‐μW/cm2 input) corresponding to a quantum yield of more than 20% electrons/photon.

Method for manufacturing semiconductor device

Abstract: PURPOSE:To manufacture a semiconductor device with a small junction-leakage current and a large current-driving capability. CONSTITUTION:In the state wherein a tungsten polyside film 17 of the gate electrode of a semiconductor device is covered with an SiO2 film, an impurity is injected into a polycrystalline Si film 45, and the impurity is diffused to an Si substrate 11 to form diffusion layers 26, 32. Thereafter, the polycrystalline Si film 45 is covered with a resist 46 to remove the SiO2 film, and then, impurity ions are implanted into the tungsten polyside film 17. Since a formation of the diffusion layers 26, 32 and the introduction of the impurity into the gate electrode are performed separately from each other, the condition of the heat treatment of the introduced impurity can be set independently of others. Therefore, the diffusion layers 26, 32 having favorable junction characteristics can be formed, and the lowering of the concentration of the impurity of the gate electrode is prevented, and further, the decrease of the gate capacity of the semiconductor device and the increase of its threshold voltage can be prevented.

Progress in long-wavelength strained-layer InGaAs(P) quantum-well semiconductor lasers and amplifiers

Abstract: The progress in long-wavelength compressively and tensile-strained InGaAs(P) quantum-well semiconductor lasers and amplifiers is reviewed. By the application of grown-in strain, the device performance is considerably improved such that conventional bulk and unstrained quantum-well active-layer devices are outperformed, while a high reliability is maintained. >

Simulation of Semiconductor Devices and Processes

Abstract: This paper will identify the reasons three-dimensional process simulators are not widely available, when three-dimensional device simulators are widely available. There appear to be four major obstacles; metrology, models, numerics, and structural barriers. Each of these will be discussed and possible solutions will be provided.

1/f noise and radiation effects in MOS devices

Abstract: An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO/sub 2/ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment. >

Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films

Abstract: A method for manufacturing a semiconductor device comprises the steps of forming a semiconductor film on a substrate, oxidizing a surface of said semiconductor film in an oxidizing atmosphere with said semiconductor film heated or irradiated with light, and further depositing an oxide film on the oxidized surface of the semiconductor film by PVD or CVD The first oxide film has a good interface condition with the semiconductor film and a characteristics of an insulated gate field effect transistor can be improved if the first oxide film and the second oxide film are used as a gate insulating film

Ion Implantation: Basics to Device Fabrication

Abstract: Preface. List of Tables. 1. Semiconductor Devices. 2. Ion Implanters. 3. Range Distribution. 4. Radiation Damage. 5. Annealing and Secondary Defects. 6. Analytical Techniques. 7. Silicon Based Devices. 8. Ion Implantation in Compound Semiconductor and Buried Layer Synthesis. Selected References. References. Index.

Semiconductor device having improved crystal orientation

Abstract: Thin-film transistors (TFTs) of peripheral logic circuits and TFTs of an active matrix circuit (pixel circuit) are formed on a single substrate by using a crystalline silicon film. The crystalline silicon film is obtained by introducing a catalyst element, such as nickel, for accelerating crystallization into an amorphous silicon film and heating it. In doing so, the catalyst element is introduced into regions for the peripheral logic circuits in a nonselective manner, and is selectively introduced into regions for the active matrix circuit. As a result, vertical crystal growth and lateral crystal growth are effected in the former regions and the latter regions, respectively. Particularly in the latter regions, the off-current and its variation can be reduced. The vertical growth and the lateral growth have a difference in the degree of crystal orientation. In general, the vertical growth does not provide so high of a degree of crystal orientation in which orientation in the (111) plane with respect to the substrate surface is dominate to a small extent. In contrast, remarkable orientation is found in the lateral growth. For example, the ratio of a reflection intensity of the (111) plane to the sum of reflection intensities of the (111), (220) and (311) planes can amount to more than 80 or 90%.

Semiconductor device including a plurality of thin film transistors at least some of which have a crystalline silicon film crystal-grown substantially in parallel to the surface of a substrate for the transistor

Abstract: Nickel is introduced to a predetermined region of a peripheral circuit section, other than a picture element section, on an amorphous silicon film to crystallize from that region. After forming gate electrodes and others, sources, drains and channels are formed by doping impurities, and laser is irradiated to improve the crystallization. After that, electrodes/wires are formed. Thereby an active matrix type liquid crystal display whose thin film transistors (TFT) in the peripheral circuit section are composed of the crystalline silicon film whose crystal is grown in the direction parallel to the flow of carriers and whose TFTs in the picture element section are composed of the amorphous silicon film can be obtained.

Method of fabricating a semiconductor device

Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200Å, thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.

Three-dimensional simulation of charge collection and multiple-bit upset in Si devices

Abstract: In this paper, three-dimensional numerical simulation is used to explore the basic charge-collection mechanisms in silicon n/sup +//p diodes. For diodes on lightly-doped substrates ( >

Semiconductor device and a fabrication process thereof

Abstract: A semiconductor device includes a package substrate and a semiconductor chip provided on the package substrate, wherein there is provided a jumper substrate carrying thereon electrodes and conductor patterns that connect the electrodes, such that the jumper substrate is mounted upon the package substrate for providing an interconnection between the electrode patterns provided on the upper major surface of the package substrate in electrical connection with the electrode pads on the semiconductor chip and the electrodes that are isolated in correspondence to the through-holes provided on the package substrate.

Method of manufacturing semiconductor device

Abstract: PURPOSE:To make an insulating film flat with high precision by a method wherein a film to be patterned which has an undercut and resist to be reversely patterned are formed on the insulating film and the resist on the insulating film and the insulating film are etched at the same time. CONSTITUTION:First and second resists 6, 8 are mutually reverse sensitivity and also when these resists 6, 8 are patterned, the identical exposing mask 7 is used with the identical position relationship. Therefore, the first resist 6 is used as a mask and is patterned, and the second resist 8 has reversed patterns with respect to that of the film to be patterned. Accordingly, when the second resist 8 and the insulating film 4 for filling steps are etched at the same time, an insulating film 4 is etched from a projecting part exposed from the second resist 8 and a recessed part coated with the second resist 8 is etched after the second resist 8 is completely removed by etching. Thus, the flatting of the insulating film 4 can be carried out with good controllability and high precision.

MOS-type semiconductor device and method of making the same

Abstract: A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 μm or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.

Method for fabricating a semiconductor device using a catalyst introduction region

Abstract: Into an amorphous silicon film, catalyst elements for accelerating the crystallization are introduced. After patterning the amorphous silicon films in which the catalyst elements have been introduced into an island pattern, a heat treatment for the crystallization is conducted. Thus, the introduced catalyst elements efficiently diffuse only inside the island-patterned amorphous silicon films. As a result, a high-quality crystalline silicon film, having the crystal growth direction aligned in one direction and having no grain boundaries, is obtained. Using the thus formed crystalline silicon film, semiconductor devices having a high performance and stable characteristics are fabricated efficiently over the entire substrate, irrespective of the size of the devices.

Optoelectronic semiconductor devices

Abstract: Basics. Semiconductor Dynamics. Junctions. Properties of Light. Light Emitting Diodes. Semiconductor Lasers. Photoconductors. P-n Diodes. Avalanche Photodiodes. Phototransistors. Materials. Technology. Packaging and Testing. Future Developments.

Method for producing crystalline semiconductor film having reduced concentration of catalyst elements for crystallization and semiconductor device having the same

Abstract: A method for producing a semiconductor film, includes the steps of: (a) forming an amorphous semiconductor film on a substrate having a surface with an insulating property; (b) introducing a material for accelerating crystallization of the amorphous semiconductor film into at least a part of the amorphous semiconductor film; (c) crystallizing the amorphous semiconductor film by heating to obtain a crystalline semiconductor film from the amorphous semiconductor film; and (d) oxidizing a surface of the crystalline semiconductor film to form a semiconductor oxide film containing a part of the material for accelerating the crystallization on the surface of the crystalline semiconductor film.

Advanced semiconductor device physics and modeling

Abstract: Semiconductor device fundamentals - energy band theory, statistics of free carriers in semiconductors, generation and recombination processes, Boltzmann transport equation, drift and diffusion mechanisms, carrier scattering mechanisms, basic semiconductor device equations, Monte Carlo simulation physics and models related to p/n junctions - description of p/n junctions, ambipolar transport equation, Linvill lumped circuit model, Sah transmission line circuit model, current and avalanche breakdown in reverse-biased junctions, tunnelling currents in p/n junctions, charge storage in p/n junctions, abrupt heterojunction diodes, abrupt heterojunctions with a setback layer, graded heterojunctions, references, problems bipolar junction transistors - steady-state characteristics under forward-active operation, current-voltage characteristics including saturation and current-induced base pushout, effect of quasineutral base width modulation, effect of nonuniform doping concentration, avalanche multiplication in bipolar transistor, multidimensional effects, poly-emitter bipolar transistors, switching speed of BJTs, large- and small-signal models, references, problems junction field-effect transistors - general theory, current-voltage characteristics of three-terminal JFETs, current-voltage characteristics of four-terminal JFETs, short-channel JFETs, large-and small-signal models, references, problems metal-oxide-semiconductor field-effect devices - metal-oxide-semiconductor (MOS) diodes, metal-oxide semiconductor field-effect transistors (MOSFET), numerical and experimental results, hot-carrier effects, capacitance of intrinsic MOSFET, MOSFET equivalent circuit, references, problems metal-semiconductor junction devices - Schottky diodes, ohmic contacts, metal-semiconductor field-effect transistors (MESFET), references, problems heterojunction bipolar and field-effect transistors - single heterojunction bipolar transistors, abrupt HBTs with a setback layer, HBTs with a graded uunction, double heterojunction bipolar transistors, heterojunction field-effect transistors, references, problems solar cells - basic concept, homojunction solar cells, heterojunction in solar cells, effect of V-groove surface on solar cell performance, references, problems photoconductive diodes - device structure and concept, general theories, conductivity and current, effect of contact regions, two-dimensional analysis, transient behaviour of photoconductive diodes, references, problems.

Power semiconductor devices for variable-frequency drives

Abstract: Advances in power semiconductor technology are the driving force for enhancement of the performance of variable-frequency motor drives. The development of power semiconductor devices with MOS-gate structures has enabled the control of large amounts of energy with very little input power. An equally important advancement has taken place in the development of improved rectifiers with reduced losses for high-frequency operation. In addition, the advent of MOS-gated power switches has led to the creation of smart power technology which makes compact systems with built-in diagnostic and protection functions commercially feasible. Although the power semiconductor chips are all made from silicon today, recent analysis has indicated that devices fabricated from silicon carbide have the potential for completely displacing silicon devices in the long range. >

Fabrication of polymer light‐emitting diodes using doped silicon electrodes

Abstract: We report the fabrication of light‐emitting diodes from the semiconducting conjugated polymer poly[2‐methoxy,5‐(2’‐ethyl‐hexyloxy)‐1,4‐phenylene‐vinylene], using doped silicon (both n and p type) as an electrode material. Light emission at low voltages is clearly demonstrated. The presence of a thin SiO2 layer at the silicon interface modifies the device characteristics compared to devices fabricated on indium‐tin‐oxide substrates. An interesting consequence of this is the ability to align the Fermi level of the silicon electrode with the lowest unoccupied molecular orbital of the polymer allowing hole injection in forward bias and electron injection in reverse bias.

Method of fabricating semiconductor devices

Abstract: A method of fabricating a semiconductor device includes the steps of forming a wiring layer on the surface of a semiconductor substrate, depositing a silicone film on the whole surface of the semiconductor substrate including the wiring layer by a CVD method and exposing the silicone film to oxidative plasma with enhanced frequencies including components of 1 MHz or less to change to a silicon oxide film, the depositing step and exposing step being alternately repeated in the same apparatus till the silicon oxide film having any desired thickness is obtained. The resulting silicon oxide film has the smooth surface and the high density.

Nonvolatile semiconductor device having charge trap film containing silicon crystal grains

Abstract: A tunnel oxide film 12 is formed on a silicon substrate 11 and a polysilicon film 16 is deposited thereon. Then, an impurity such as phosphorus or the like is doped into the polysilicon film 16 and the polysilicon film 16 is subjected to thermal oxidation. As a result, a charge trap film 15 in which silicon grains 13 in the inside of the polysilicon film 16 are coated with a thermal oxide film 14 is obtained. If necessary, a multilayer charge trap film 15 is obtained by repetition of the foregoing steps. Since the thermal oxide film 14 has an excellent insulating property compared with an oxide film obtained by a sputtering or CVD method and therefore the charge trap film 15 has a high dielectric withstanding voltage. Further, since the silicon grains 13 coated with the thermal oxide film 14 have a deep trap level, an improved signal charge holding property can be obtained. Thereby, it is provided a nonvolatile semiconductor storage device comprising a charge trap film having a deep trap level and an improved dielectric withstanding voltage.

A semiconductor device with optical waveguides to achieve signal transmission using optical means

Abstract: A semiconductor device (30) is configured with a transparent insulator substrate (31) in which an optical waveguide(s) (37) is formed, a semiconductor thin film (32) is pasted on the transparent insulator substrate (31), an integrated circuit(s) (33) is formed on the semiconductor thin film (32), a light emitting device(s) (34) is connected to the wiring of the integrated circuit (33), and a light detecting device(s) (36) is optically connected to the light emitting device(s) (34) via the optical waveguide(s) (37). Some wiring segments of the integrated circuit (33) are thereby replaced with the optical waveguide(s) (37) so as to optically transmit signals.

Low-loss, single-model optical phase modulator in SIMOX material

Abstract: This paper reports results of the simulation of an optical phase modulator. The proposed modulator consists of an elongated p-i-n structure fabricated in a silicon-on-insulator material such as SIMOX. It utilizes the free-carrier effect to produce the desired refractive index change in a single-mode optical rib waveguide. The MEDICI two-dimensional semiconductor device simulation package has been employed to optimize the overlap between the injected free carriers and the propagating optical guided mode. Although the device is designed to support a single optical guided mode, it measures several micrometers in cross-sectional dimensions, thereby simplifying fabrication and allowing efficient coupling to/from other single-mode devices. Furthermore, the device has an extremely high figure of merit, predicting over 200/spl deg/ of induced phase shift per volt per millimeter, as well as a low drive current of less than 10 mA. This is approximately an order of magnitude lower than most other reported devices in silicon. >

Semiconductor device having vertical conduction transistors and cylindrical cell gates

Abstract: A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.

A simple edge termination for silicon carbide devices with nearly ideal breakdown voltage

Abstract: In this paper, a simple edge termination is described which can achieve near ideal parallel plane breakdown for silicon carbide devices. This novel edge termination involves self aligned implantation of a neutral species on the edges of devices to form an amorphous layer. With this termination formed using argon implantation, the breakdown voltage of Schottky barrier diodes was measured to be very close to ideal plane parallel breakdown voltage. >

Improved charge control and frequency performance in InAs/AlSb-based heterostructure field-effect transistors

Abstract: We demonstrate high-speed InAs/AlSb-based heterostructure field-effect transistors (HFET's) displaying greatly improved charge control properties and enhanced high-frequency gate performance. Microwave devices with a 0.5/spl times/84 /spl mu/m/sup 2/ exhibit a peak unity current gain cut-off frequency of f/sub T/=93 GHz. The HFET usable operational range was extended to V/sub DS/=1.5 V (from V/sub DS/=0.4-0.5 V) thus greatly enhancing the applicability of InAs/AlSb-based HFET's for low-power, high-frequency amplification. We also report on the bias dependence of f/sub T/, and demonstrate that InAs/AlSb-based HFET's offer an attractive frequency performance over an adequately wide range of drain biases. >

Semiconductor Devices: An Introduction.

Abstract: The revolution of solid state electronics quantum mechanics and statistical physics of electrons structure of the semi-conductors electrons in crystalline materials - semi-conductor bandstructure doping of semi-conductors transport and optical properties in semi-conductors semi-conductors - the material of choice for active devices junctions in semi-conductors - P-N diodes metal-semiconductor and insulator-semiconductor junctions bipolar junction transistors field effect transistors negative impedence microwave diodes opto-electronic devices - photons to electrons opto-electronic devices - light emission and modulation crystal growth and device fabrication.

Manufacture of semiconductor device

Abstract: PURPOSE:To perfectly complete the etching of a polyimide film which may be used as a protection film by removing a large stepped area at the end of scribe line. CONSTITUTION:A silicon nitride film 15 as a first protection film and a polyimide film 16 as a second protection film are formed in lamination in this sequence on the entire surface of a semiconductor substrate 11 on which semiconductor elements and wirings are formed, the polyimide film 16 on an aluminum film 14 at the end of the scribe line is removed by selective etching and thereafter a silicon nitride film 15 on the aluminum film 14 is removed by selective etching.

Thin film semiconductor device including a driver and a matrix circuit

Abstract: A thin film transistor including a thin semiconductor film which has a central portion as a channel region, with the side portions of the semiconductor film except for the channel region being a source and a drain regions which includes n-type impurities such as phosphorus ions of high concentration (3×10 15 atoms/cm 2 ), and a low concentration region provided between the channel region and each of the source and drain regions including p-type impurities such as boron ions of a low concentration (1×10 13 atoms/cm 2 ) whereby the low concentration region serves to reduce the off current.