Showing papers on "Snapback published in 1999"

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Snapback and safe operating area of LDMOS transistors

Abstract: This paper deals with the measurement and prediction of the SOA boundary and the accompanying device physics. Results are given for n-channel LDMOS transistors having a self-aligned body diffusion. LDMOS SOA has been discussed previously in a number of papers, however, there is still a need for improving the overall understanding of this rather complicated subject. To be complete, thermal effects should also be included in the definition of SOA, however, these can be treated separately and we focus here on the "electrical SOA", which is defined by the Id-Vds boundary where snapback occurs.

Analysis of snapback behavior on the ESD capability of sub-0.20 /spl mu/m NMOS

Abstract: The self-biased lateral NPN (LNPN) operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined. The effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mu/m, and 0.25 /spl mu/m. Specifically, the influence of gate oxides <30 /spl Aring/, and the effects of CoSi/sub 2/ and TiSi/sub 2/ are characterized with the purpose of defining process dependencies and design space. It is shown that as gate oxides get thinner, oxide breakdown may become a limiting factor depending on the LNPN properties. Furthermore, changes in LNPN current gain through process or design variations, and the substrate resistance, can be used to tune ESD performance. Hence, transistor design and process choices can be made to ensure that the LNPN is optimized for successful operation even for very thin gate oxides in sub-0.2 /spl mu/m technologies.

An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

Abstract: In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 /spl mu/m, 35 /spl Aring//70 /spl Aring/ dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over nonSI and SI I/O pad designs, respectively.

An analytical model of positive HBM ESD current distribution and the modified multi-finger protection structure

Abstract: In order to study the ESD zapping current distribution variation with the well pick-up layout, a new transmission-line equivalent-circuit model is proposed which includes the effects of parasitic bipolar transistors and the horizontal and vertical P-well resistance. Based on this equivalent circuit and from real-time I-V characteristics during ESD zapping (Duvvury and Diaz, 1992), an analytical solution can be derived. For conventional multi-finger structures, it shows that the maximum current or power density of the device under the ESD zapping event is located at the region near the P-well pick-up. This model prediction is consistent with the device's damage sites after ESD zapping. Based on this model, a novel protection structure leading to uniform current distribution can be achieved by inserting P/sup +/ diffusion into each source region of NMOS devices. From the real-time I-V characteristics during ESD zapping, a new phenomenon termed the self-biasing effect is also observed. In order to sustain sufficient substrate potential to keep the bipolar turn-on, the device's snapback voltage should increase to generate more impact ionization current when the effective substrate resistance decreases. We observed the phenomenon that snapback voltage is varied with the device layout. As a result, higher snapback voltage may not lead to lower ESD threshold voltage.

Substrate pumped ESD network with trench structure

Abstract: An ESD protection circuit which may be implemented in thin epitaxial substrate surfaces. The protection device includes a MOSFET transistor or bipolar transistor implemented in a trench isolated area of the substrate. The isolation of the MOSFET transistor permits the substrate region to be pumped with an electric charge which reduces the trigger/snapback voltage and MOSFET threshold voltage for the device. A trigger current supplies the pumping current to the isolated substrate area when a transient voltage is applied thus lowering the trigger/snapback voltage of the MOSFET transistor in the presence of a transient voltage.

NMOS electrostatic discharge protection device and method for CMOS integrated circuit

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides

Abstract: Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal. In response to the current flow through the inter-transistor node, the lateral bipolar transistor substantially increases the current flow from the first terminal, through the lateral bipolar transistor, and to the second terminal so that a majority of current will flow through this path. Similarly, when an ESD pulse appears on the second terminal, this creates current flow from the second terminal, through the collector-base junction of the lateral bipolar transistor, through the inter-transistor node, through the diode, and to the first terminal.

A high accuracy power MOSFET SPICE behavioral macromodel including the device self-heating and safe operating area simulation

Abstract: The new analog behavioral modeling features of modern SPICE simulators were used to develop a high accuracy power MOSFET macromodel, that considers the electrothermal processes and simulates the device behavior beyond the safe operating area (SOA) limits. New static equations were implemented with "in-line equation" controlled sources, in order to accurately simulate the device on-state voltage and forward transconductance. The model gives a precise description of the parasitic interelectrode capacitances, that were piecewise-linear approximated with "look-up table" controlled sources. The SOA was simulated by including the device avalanche breakdown and snapback effect. The model's parameters extraction was greatly simplified and the resulting model is portable to all the modern SPICE simulators. The simulations performed for different types of commercial power MOSFETs proved an excellent agreement with the data-sheet characteristics, giving also a reasonable analysis time, with no convergence problems.

A novel dual-direction IC ESD protection device

Abstract: We report the design of a novel dual-direction on-chip IC electrostatic discharge (ESD) protection device. The design was predicted by simulation, matched by measurements and features a high ESD-Si ratio of /spl sim/80 V//spl mu/m, deep snapback, low R/sub on/ of 0.64 /spl Omega/, low leakage (/spl sim/pA), adjustable triggering voltage, and good scalability.

A compact model for the N-well resistor

Abstract: A simple and compact model is derived for the n-well resistor. The model was derived specifically for use in simulation and design of ESD protection circuits using SPICE. Hence it encompasses three regions of resistor operation: linear and velocity saturation, avalanche multiplication and snapback and high injection. Excellent fit with experimental data is found.

A low-triggering circuitry for dual-direction ESD protection

Abstract: A novel low-triggering, dual-direction on-chip Electrostatic Discharge (ESD) protection circuitry is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions The compact circuit features low triggering (75 V), short response time (<1 ns), symmetric deep snapback I-V characteristics, and low on-resistance (/spl sim//spl Omega/) It passed 14 kV HEM ESD test and is very area efficient (80 V//spl mu/m) The design was predicted by simulation that fits measurement

Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices

Abstract: Breakdown homogeneity and triggering of bipolar transistor action are studied in smart power technology ESD protection devices via measurements of temperature distribution and thermal dynamics by a laser interferometric technique. Temperature changes in the devices biased in the avalanche multiplication or snapback region are monitored by ns-time scale measurements of the optical phase shift. The distribution of the temperature-induced phase shift is correlated with the position of ESD damage obtained by backside IR microscopy.

Reproducibility of transmission line measurement of bipolar I-V characteristics of MOSFETs

Abstract: Reproducibility of transmission line (TL) measurement of bipolar current-voltage (I-V) characteristics of grounded gate MOSFET's has been examined. It is observed that the reproducibility is related to the duration of the pulses generated by the transmission line, and a longer pulse duration gives a better reproducibility. For a short pulse duration, it is more difficult to reproduce the I-V characteristics in the triggering region than in other regions (i.e., the pretriggering and snapback regions).

Studies of decay and snapback effects on lhc dipole magnets

Abstract: 1LHC model magnets have dynamic field imperfections of various nature. Two effects of particular importance are field component decay during injection and ''snapback'' during the first few seconds of acceleration, which happens over typically 15 to 20 mT. The dynamic behaviour of the model magnets was measured as a function of several parameters in the operation cycle and powering history. We demonstrate how the systematic variation of only one single operation cycle parameter can affect the behaviour of the sextupole component.

A novel dual gated lateral MOS-bipolar power device

Abstract: A novel CMOS compatible lateral dual gated MOS-bipolar transistor (DGMBT) is demonstrated through experiments. The device is configured by a parallel combination of an LDMOS and an LIGBT. The device can be made to operate in different modes by controlling the low voltage bias on the LDMOS and the LIGBT gates. In the mixed mode, unlike an anode shorted LIGBT, this device shows a smooth transition from the MOSFET mode to a bipolar mode without any snapback. By controlling the gate bias at the LIGBT end, the level of injection can be controlled. The anode short ensures that the device turns off much faster than a conventional LIGBT.

Supply Voltage Limits in Standard CMOS Technologies

Abstract: Various undesirable effects can take place in a low-voltage transistor if one of its terminals is pushed beyond the voltage limit set by the technology. The scope of this chapter is the investigation and modelling of these effects. A particular interest is first focused on the degradation of the device characteristics resulting from channel hot-carrier effects. Then, destructive mechanisms such as, avalanche breakdown. surface breakdown, snapback breakdown, punchthrough breakdown and gate oxide breakdown are analysed. These theoretical considerations are the basics required to implement the design of reliable high-voltage devices.

A robust curve tracing scheme for the simulation of bipolar breakdown characteristics with nonlocal impact ionization models

Abstract: The authors propose a robust curve tracing scheme for the simulation of the complete Ic(Vce)|Is=0 breakdown characteristic of a bipolar transistor including snapback effects. Compared to classical curve tracing schemes, this new algorithm does not require the complete Jacobian matrix and/or external resistors of arbitrary size at the device contacts. Therefore it allows the application of nonlocal impact ionization models for the evaluation of bipolar breakdown characteristics.

Analytical Model of Human Body Model Electrostatic Discharge Current Distribution and Novel Electrostatic Discharge Protection Structure

Abstract: Conventionally, the n-p-n bipolar transistor with a substrate resistor operated in the snapback region has been the basic model used to explain the discharge behavior of a lightly doped drain (LDD) N-channel metal-oxide semiconductor (NMOS) transistor under a positive human-body model (HBM) electrostatic discharge (ESD) zapping event. However, this simple model ignores the geometry effect by the P-well pick-up position and does not explain the current-crowding effect. In this paper, a new transmission-line equivalent-circuit model with the equal-potential-region (EPR) formation is proposed to study the ESD zapping current distribution. The simulation result shows that maximum current density is in the region near the P-well pick-up, which corresponds to the damage sites determined by failure analysis. Based on this new model, a novel protection structure with P+ diffusion in each source region is proposed to improve current uniformity, which is verified to have an excellent ESD failure threshold. In addition, from the measurement of real-time current–voltage (I–V) characteristics during ESD zapping, a phenomenon called the self-biasing Effect is observed. When the effective substrate resistance decreases, the device's snapback voltage will inherently increase to generate more impact ionization current so as to sustain a sufficient substrate potential to keep the bipolar turned on. However, this Vsp increase will not necessarily lead to a lower ESD failure threshold.

Study of bipolar transistor action during ESD stress in smart power ESD protection devices using interferometric temperature mapping

Abstract: Thermal dynamics, temperature distribution and bipolar transistor triggering during electrostatic discharge (ESD) events are studied in smart-power technology ESD protection devices by a backside inteiferometric technique. Temperature changes in the device active area are monitored via ns-time scale measurements of optical phase shift. The bipolar transistor action under snapback operation is identified by a dominant phase shift signal arising in the n+-emitter region. Hot spot formation and temperature inhomogeneities due to current crowding are studied as a function of device layout and power.

CMOS ESD protection circuits utilizing submicron transistors operating in the snapback mode

Abstract: The advancement of CMOS IC technologies presents increasing challenges in the design of reliable electrostatic discharge (ESD) protection. This paper presents novel CMOS ESD protection circuits using submicron MOS devices in the snapback region of operation. The measured characteristics of these ESD circuits are compared to simulations in HSPICE using previously developed models of MOS transistors in snapback.