Showing papers on "Strained silicon published in 1998"

Silicon single-electron quantum-dot transistor switch operating at room temperature

Abstract: We fabricated a silicon single-electron quantum-dot transistor, which showed drain current oscillations at room temperature. These oscillations are attributed to electron tunneling through a single silicon quantum dot inside a narrow wire channel. Analysis of its current–voltage characteristic indicates that the energy level separation is about 110 meV and the silicon dot diameter is about 12 nm.

Parasitic charging of dielectric surfaces in capacitive microelectromechanical systems (MEMS)

Abstract: Silicon dioxide and silicon nitride coatings are preferably used as dielectric layers for short-circuit protection in capacitive silicon microsensors and microactuators. However, their tendency to electrostatic charging can diminish the device reliability. Gas discharges in the air gap of silicon cantilever actuators have been observed, resulting in surface charge accumulation on the electrode passivation of the devices. Charge decay characteristics were recorded for a silicon oxide passivation and a multilayer passivation by silicon oxide and silicon nitride. The charges are found to be highly stable in time. Based on these observations, rules for the application and design of dielectric layers in microdevices are proposed.

A “smarter-cut” approach to low temperature silicon layer transfer

Abstract: Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted silicon layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a silicon layer from a silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

Interface structure between silicon and its oxide by first-principles molecular dynamics

Abstract: The requirement for increasingly thin (<50 A) insulating oxide layers in silicon-based electronic devices highlights the importance of characterizing the Si–SiO2 interface structure at the atomic scale. Such a characterization relies to a large extent on an understanding of the atomic-scale mechanisms that govern the oxidation process. The widely used Deal–Grove model invokes a two-step process in which oxygen first diffuses through the amorphous oxide network before attacking the silicon substrate, resulting in the formation of new oxide at the buried interface1. But it remains unclear how such a process can yield the observed near-perfect interface2,3,4,5,6,7,8,9,10,11,12. Here we use first-principles molecular dynamics13,14,15 to generate a model interface structure by simulating the oxidation of three silicon layers. The resulting structure reveals an unexpected excess of silicon atoms at the interface, yet shows no bonding defects. Changes in the bonding network near the interface occur during the simulation via transient exchange events wherein oxygen atoms are momentarily bonded to three silicon atoms — this mechanism enables the interface to evolve without leaving dangling bonds.

Gas-sensing semiconductor devices

Abstract: A gas-sensing semiconductor device (1) is fabricated on a silicon substrate (2) having a thin silicon oxide insulating layer (3) on one side and a thin silicon layer (4) on top of the insulating layer (3) using CMOS SOI technology. The silicon layer (4) may be in the form of an island surrounded by a silicon oxide insulating barrier layer (4) formed by the known LOCOS oxidation technique, although other lateral isolation techniques may also be used. The device (1) includes at least one sensing area provided with a gas-sensitive layer (18), a MOSFET heater (6) for heating the gas-sensitive layer (18) to promote gas reaction with the gas-sensitive layer (18) and a sensor (16), which may be in the form of a chemoresistor, for providing an electrical output indicative of gas reaction with the gas-sensitive layer (18). As one of the final fabrication steps, the substrate (2) is back-etched so as to form a thin membrane (20) in the sensing area. Such a device can be produced at low cost using conventional CMOS SOI technology.

Method of etching silicon nitride by a mixture of CH2 F2, CH3F or CHF3 and an inert gas

Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH 2 F 2 , CH 3 F, or CHF 3 and an inert gas to the dry etching atmosphere Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO 2 can be enhanced and also etching anisotropy can be enhanced

Pseudo silicon on insulator MOSFET device

Abstract: A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer

Abstract: An integrated CMOS circuit, and method for producing same, including a semiconductor substrate having a p-channel MOS transistor and an n-channel MOS transistor formed therein and having a first silicon layer, a stressed Si 1-x Ge x layer and a second silicon layer which are preferably grown by selective epitaxy. In an ON state, a buried channel is formed in the stressed Si 1-x Ge x layer in the p-channel MOS transistor and a surface channel is formed in the second silicon layer in the n-channel MOS transistor.

Use of crystalline SiOx barriers for Si-based resonant tunneling diodes

Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10−4 to about 10−7 until the silicon oxide layer has reached a predetermined thickness. In the case of a tunneling diode, the layer of silicon oxide has a thickness of from about 2 to about 8 monolayers and the layer of crystallographic silicon has a thickness of from about 2 to about 8 monolayers. A second layer of silicon oxide is provided on the layer of silicon remote from the layer of crystallographic silicon oxide. In the case of a silicon-on-insulator-type structure, the layer of crystallographic silicon oxide is from about 500 to about 2000 Angstroms and preferably 1000 Angstroms and the layer of silicon is from about 50 to about 1000 Angstroms and preferably 100 Angstroms.

Method and apparatus for self-doping negative and positive electrodes for silicon solar cells and other devices

Abstract: A self-doping electrode to silicon is formed primarily from a metal (major component) which forms a eutectic with silicon. A p-type dopant (for a positive electrode) or an n-type dopant (for a negative electrode) is alloyed with the major component. The alloy of major component and dopant is applied to a silicon substrate. Once applied, the alloy and substrate are heated to a temperature above the major component-silicon eutectic temperature such that the major component liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature permitting molten silicon to reform through liquid-phase epitaxy and while so doing incorporate dopant atoms into its regrown lattice. Once the temperature drops below the major component-silicon eutectic temperature the silicon, which has not already regrown into the lattice, forms a solid-phase alloy with the major component and the remaining unused dopant. This allow of major component, silicon and unused dopant is the final contact material. Alternatively, a self-doping electrode may be formed from an unalloyed metal applied to a silicon substrate. The metal and substrate are heated to a temperature above the metal-silicon eutectic temperature in an ambient gas into which a source of vaporized dopant atoms has been introduced. Dopant atoms in the ambient gas are absorbed by the molten mixture of metal-silicon to a much greater extent than they are absorbed by the solid silicon substrate surfaces. The temperature is then decreased to below the metal-silicon eutectic temperature. During this temperature decrease, the doped regrown silicon layer and the metal-silicon alloy final contact material are created in the same process as described above.

Lightly nitridation surface for preparing thin-gate oxides

Abstract: A method for forming a dielectric layer upon a silicon layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon layer. There is then formed through use of a first thermal annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material silicon nitride containing layer upon a partially consumed silicon layer derived from the silicon layer. There is then oxidized through use of a second thermal annealing method employing an oxidizing material containing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer upon a further consumed silicon layer derived from the partially consumed silicon layer. The method is particularly useful in forming a gate dielectric layer with enhanced hot carrier resistance properties and enhanced dopant diffusion barrier properties within a field effect transistor (FET).

Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region

Abstract: Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

Method of fabricating a fully self-aligned TFT-LCD

Abstract: An ITO layer and a first metal layer is patterned on a glass substrate. A first silicon nitride layer, a silicon layer and a second silicon nitride layer are formed on the substrate. A back-side exposure is introduced using the gate electrodes as a mask. The second silicon nitride layer that is not covered by a positive photoresist is etched. A heavily doped silicon layer is formed over the substrate. A negative photoresist is formed over the heavily doped silicon layer. Then, a further back-side exposure is employed. The heavily doped silicon layer over the etched second silicon nitride layer is removed. Via holes are created to expose a portion of the first metal layer. A second metal layer and a third metal layer are respectively formed. Next, a thermal annealing is performed for forming silicide. Subsequently, a third metal layer and the second metal layer are patterned. Then, the island pattern is defined. Subsequently, a passivation layer formed of silicon nitride layer is deposited on the island pattern.

Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively

Abstract: The process consists in depositing, by chemical vapor deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450° C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.

Semiconductor processing method of providing a doped polysilicon layer

Abstract: A semiconductor processing method of providing a doped polysilicon layer atop a substrate includes, a) depositing a layer of substantially amorphous silicon having a dopant concentration of less than or equal to about 1×10 16 atoms/cm 3 over a substrate to a thickness of less than or equal to about 30 Angstroms; b) depositing a layer of silicon over the amorphous silicon layer in a manner which in situ dopes such layer to a dopant concentration of greater than about 1×10 16 atoms/cm 3 ; and c) providing the deposited silicon layers to be polycrystalline. Preferably, the substantially amorphous layer is entirely undoped as-deposited. The invention is believed to have greatest applicability to provision of thin film doped polysilicon layers having thicknesses of less than or equal to about 100 Angstroms. Accordingly, the combined thickness of the deposited silicon layers is preferably less than or equal to about 100 Angstroms. The preferred method for providing the deposited silicon layers to be polycrystalline is by rapid thermal processing. Such, or other processing, also effectively dopes the first deposited silicon layer by out-diffusion from the second deposited layer.

Growth of silicon oxide on hydrogenated silicon during lithography with an atomic force microscope

Abstract: We present an experimental study of growth of silicon oxide strips drawn on hydrogenated silicon under the voltage biased tip of an atomic force microscope operating in ambient atmosphere. Oxide formation was found to occur at negative tip biases above a voltage threshold around |−2|V, corresponding to the minimum electric field required for hydrogen removal from the substrate surface. We show the influence of tip-sample distance and of the chemical composition of the atmosphere on the growth. An ozone enriched atmosphere leads to a growth kinetics enhancement.

Silicon implantation into selective areas of a refractory metal to reduce consumption of silicon-based junctions during salicide formation

Abstract: An integrated circuit fabrication process is provided for implanting silicon into select areas of a refractory metal to reduce the consumption of silicon-based junctions underlying those select areas during salicide formation. The refractory metal is subjected to a heat cycle to form salicide upon the junctions and polycide upon the upper surface of a gate conductor positioned between the junctions. In response to being heated, the metal atoms readily react with implanted silicon atoms positioned proximate the metal atoms to form salicide. Once a metal atom has reacted with implanted silicon atoms, it is no longer available to react with silicon atoms of the junctions. However, not all of the metal atoms react with implanted silicon atoms, so some of the metal atoms are free to react with the silicon atoms of the junctions. Interdiffusion and reaction between those available metal atoms and those silicon atoms of the junctions occurs as a result of heating the semiconductor topography. The junctions thus may be partially consumed, ensuring that a low resistance pathway is formed between the salicide and the junctions. Advantageously, the remaining portions of the junctions are sufficiently large to prevent junction spiking entirely through the junctions to the bulk substrate underlying the junctions. In fact, so little of the junctions are consumed during salicide formation that the junction depth may be minimized without suffering increased junction leakage due to junction spiking.

Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits

Abstract: A method for fabricating a plurality of shallow-junction metal oxide semiconductor field effect transistors (MOSFETs) which are separated by substantially transparent isolation elements (102). This method includes the amorphization of a selected depth of silicon (200) in a silicon wafer. A top layer stack of a dielectric and a highly radiation absorbent material are deposited to protect areas of which amorphization is not desired. After the melted silicon has cooled and recrystallized, the top layer of highly absorbent material is removed.

Initial stages in the carbonization of (111)si by solid-source molecular beam epitaxy

Abstract: Silicon carbide can be reproducibly grown on (111)Si below 600 °C by carbonization using an elemental solid carbon source in molecular beam epitaxy. The initial stages were observed by in situ reflection high-energy electron diffraction. Prior to silicon carbide growth, the continuous carbon flux lead to a transition from the (7×7) reconstruction of clean (111)Si to a carbon-induced (∛×∛)R30° structure. Above 660 °C, the silicon carbide growth starts directly on the silicon surface via three-dimensional nucleation. Below 660 °C, first a thin silicon–carbon alloy was formed by diffusion of carbon into the surface near the region with a concentration exceeding the bulk solubility in silicon.

Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications

Abstract: A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer. Patterning, or CMP, of the doped HSG silicon layer, and of the heavily doped amorphous silicon layer, results in the creation of a storage node electrode. The use of the composite buffer layer allows the growth of an undoped HSG silicon layer to be achieved, thus maximizing uniformity and HSG silicon roughness, while the anneal cycle, applied to the undoped HSG silicon layer, results in the attainment of the doped HSG silicon layer, offering reduced capacitance depletion compared to undoped HSG silicon counterparts.

Production of silicon single crystal and silicon single crystal wafer

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing a high-quality silicon single crystal having no growth defect in the whole region of wafer and slight variation of precipitated amount of oxygen by pulling up the crystal while controlling a pulling up speed being a variable having both commonality and generality and to obtain the silicon single crystal produced by the method. SOLUTION: In a method for growing a silicon single crystal by a czochralski method, a crystal pulling up speed is controlled to grow the crystal while controlling the speed between a transition pulling up speed Pc at which a transition from a zone in which an atomic vacancy is excessive but no growth defect exists to a zone in which an interstitial silicon atom is excessive but no its aggregate exists occurs and a transition pulling up speed Pi at which a transition from a zone in which an interstitial silicon atom is excessive but no its aggregate exists to a zone in which the aggregate of the interstitial silicon atom exists occurs. The silicon single crystal is obtained by the method. A silicon single crystal wafer is obtained from the silicon single crystal. COPYRIGHT: (C)1999,JPO

Air-gap amorphous silicon thin film transistors

Abstract: Top gate and bottom gate amorphous silicon thin film transistors where the dielectric has been replaced by an air gap have been fabricated on glass substrates using surface micromachining techniques. Bridges were formed by using low density silicon nitride as a sacrificial layer. In bottom gate structures the bridge material was amorphous silicon and in top gate structures it was highly doped n+ microcrystalline silicon. The first working devices show transistor behavior with field effect mobilities between 0.1 and 0.5 cm2 V−1 s−1.

Hybrid polycrystalline and amorphous silicon structures on a shared substrate

Abstract: Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.

Thin-beam bulk micromachining based on RIE and xenon difluoride silicon etching

Abstract: A new process for fabricating thin mechanical beam structures from single-crystal silicon has been developed. Lateral and vertical dimensions of the beam can be precisely defined. The beam is positioned in the middle of a silicon wafer at exactly equal distances from both sides. The beam design is not limited by crystal orientations of silicon. The silicon beam structure is essentially stress free because the whole structure is made of uniformly doped single-crystal silicon. This thin-beam process offers significantly expanded design freedom to bulk silicon micromachining. Additionally, a silicon dioxide structure with very high aspect ratio has been fabricated with a similar technique.

Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction

Abstract: The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as an anti-reflective coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the oxide layer are patterned to form ultra short channel polysilicon gates. A thermal annealing is performed to recover the etching damage in the substrate and generate a pad oxide layer on the surface of the polysilicon gate and the substrate. An nitrogen-doped amorphous silicon layer is formed on the gate structure and on the pad oxide. Next, an ion implantation is carried out to dope dopants into the gate and substrate, thereby forming source and drain. A steam oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon dioxide layer. Simultaneously, an ultra-shallow extended source and drain junction adjacent to the gate structure is obtained by using the amorphous silicon layer as a diffusion source. Subsequently, the nitrogen-doped silicon dioxide layer is etched back to form oxide spacers. Then, the cap silicon nitride layer are removed. Then, two-step silicidation process are used to form silicided contacts.

Porous silicon dioxide insulator

Abstract: A porous silicon dioxide insulator having a low relative dielectric constant of about 2.0 or less is formed from a silicon carbide base layer. Initially, at least one layer of silicon carbide is deposited on a semiconductor substrate. The silicon carbide layer is then etched to form a porous silicon carbide layer, which is oxidized to produce the final porous silicon dioxide layer.

Method for growing high-quality crystalline Si quantum wells for RTD structures

Abstract: A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic perovskite material (5) is formed over the silicon substrate and substantially matched to the lattice constant of the silicon substrate. A layer of crystallographic silicon (7) is formed over the perovskite layer substantially matched to the lattice constant of the perovskite layer. The perovskite layer is formed by the steps of placing the silicon substrate in a chamber and then evaporating a layer of barium strontium oxide (3) thereon with a thickness of from about three to about six Angstroms and then evaporating a layer of calcium strontium titanate (5) thereon having a thickness of from about six to about 25 Angstroms thereon in the case of a tunneling diode. A second layer of silicon oxide (9) is provided on the layer of silicon remote from the perovskite layer.

Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure

Abstract: A process creating a crown shaped storage node electrode, for high density, DRAM designs, has been developed. The process features the formation of an hemispherical grain, (HSG), silicon layer, only on the outside walls of the amorphous silicon vertical shapes, of the crown shaped storage node electrode. The HSG silicon layer is formed from HSG silicon seeds, and from undoped, or lightly doped amorphous silicon layers, or a combination of both. The amorphous silicon vertical shapes are comprised of an undoped, or lightly doped amorphous silicon layer, placed as the outside layer, while a heavily doped amorphous silicon layer is used for the inside layer. This configuration therefore only allows the formation of the HSG silicon layer on the outside walls of the amorphous silicon vertical shape, and therefore results in a crown shaped storage node electrode, with a minimum space between vertical shapes maintained, and not compromised by encroaching HSG silicon layers, that would have been formed on the inside surfaces of the vertical shapes, if a heavily doped amorphous silicon layer were not present.