Showing papers on "Strained silicon published in 2001"

An efficient room-temperature silicon-based light-emitting diode.

Abstract: There is an urgent requirement for an optical emitter that is compatible with standard, silicon-based ultra-large-scale integration (ULSI) technology. Bulk silicon has an indirect energy bandgap and is therefore highly inefficient as a light source, necessitating the use of other materials for the optical emitters. However, the introduction of these materials is usually incompatible with the strict processing requirements of existing ULSI technologies. Moreover, as the length scale of the devices decreases, electrons will spend increasingly more of their time in the connections between components; this interconnectivity problem could restrict further increases in computer chip processing power and speed in as little as five years. Many efforts have therefore been directed, with varying degrees of success, to engineering silicon-based materials that are efficient light emitters. Here, we describe the fabrication, using standard silicon processing techniques, of a silicon light-emitting diode (LED) that operates efficiently at room temperature. Boron is implanted into silicon both as a dopant to form a p-n junction, as well as a means of introducing dislocation loops. The dislocation loops introduce a local strain field, which modifies the band structure and provides spatial confinement of the charge carriers. It is this spatial confinement which allows room-temperature electroluminescence at the band-edge. This device strategy is highly compatible with ULSI technology, as boron ion implantation is already used as a standard method for the fabrication of silicon devices.

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

Abstract: We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Method for forming a high dielectric constant material

Abstract: Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs

Abstract: A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, ie, SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs) This fabrication technique is based on the high-temperature oxidation of the SGOI layers with a lower Ge fraction It is found that Ge atoms are rejected from the oxide and condensed in the SGOI layers The conservation of the total amount of Ge atoms in the SGOI layer is confirmed by structural and compositional analyses of dry-oxidized SGOI layers at 1050°C of different initial thicknesses and oxidation times Using this technique, a 16-nm-thick SGOI layer with the Ge fraction as high as 057 is successfully obtained The Ge profiles across the SGOI layers are quite uniform and the layers are almost completely relaxed Significant dislocation generation in the SGOI layer is not observed after the oxidation This is a promising technique for application to sub-100 nm fully-depleted silicon-on-insulator (SOI) MOSFETs with strained-Si or SiGe channels

Buried channel strained silicon FET using a supply layer created through ion implantation

Abstract: A buried channel FET including a substrate, a relaxed SiGe layer, a channel layer, a SiGe cap layer, and an ion implanted dopant supply. The ion implanted dopant supply can be in either the SiGe cap layer or the relaxed SiGe layer. In one embodiment the FET is a MOSFET. In another embodiment the FET is within an integrated circuit. In yet another embodiment, the FET is interconnected to a surface channel FET.

Process for fabricating thin film transistors

Abstract: Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

Strained silicon on insulator structures

Abstract: A SOI structure and a method for its fabrication, in which a strained silicon layer lies directly on an insulator layer, contrary to the prior requirement for strained-Si layers to lie directly on a strain-inducing (e.g., SiGe) layer. The method generally entails the forming a silicon layer on a strain-inducing layer so as to form a multilayer structure, in which the strain-inducing layer has a different lattice constant than silicon so that the silicon layer is strained as a result of the lattice mismatch with the strain-inducing layer. The multilayer structure is then bonded to a substrate so that an insulating layer is between the strained silicon layer and the substrate, and so that the strained silicon layer directly contacts the insulating layer. The strain-inducing layer is then removed to expose a surface of the strained silicon layer and yield a strained silicon-on-insulator structure that comprises the substrate, the insulating layer on the substrate, and the strained silicon layer on the insulating layer. As a result, the method yields a strained silicon-on-insulator (SSOI) structure in which the strain in the silicon layer is maintained by the SOI structure.

Minimally- patterned, thin-film semiconductor devices for display applications

Abstract: A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer, having a thickness less than approximately 40 nm. The shared silicon layer extends continuously between the first and second transistors. The silicon layer may consist of unpatterned silicon. Heavily doped material may not be required at metal-silicon contact interfaces.

Method for forming dielectric stack without interfacial layer

Abstract: A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800° C. and about 1000° C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Computational design of direct-bandgap semiconductors that lattice-match silicon

Abstract: Crystalline silicon is an indirect-bandgap semiconductor, making it an inefficient emitter of light. The successful integration of silicon-based electronics with optical components will therefore require optically active (for example, direct-bandgap) materials that can be grown on silicon with high-quality interfaces. For well ordered materials, this effectively translates into the requirement that such materials lattice-match silicon: lattice mismatch generally causes cracks and poor interface properties once the mismatched overlayer exceeds a very thin critical thickness. But no direct-bandgap semiconductor has yet been produced that can lattice-match silicon, and previously suggested structures1 pose formidable challenges for synthesis. Much recent work has therefore focused on introducing compliant transition layers between the mismatched components2,3,4. Here we propose a more direct solution to integrating silicon electronics with optical components. We have computationally designed two hypothetical direct-bandgap semiconductor alloys, the synthesis of which should be possible through the deposition of specific group-IV precursor molecules5,6 and which lattice-match silicon to 0.5–1% along lattice planes with low Miller indices. The calculated bandgaps (and hence the frequency of emitted light) lie in the window of minimal absorption in current optical fibres.

CMOS with strained silicon channel NMOS and silicon germanium channel PMOS

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel

Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

CMOS inverter circuits utilizing strained silicon surface channel MOSFETS

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOFSET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Silicon carbide CMOS channel

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon carbide channel layer on the substrate. A silicon layer is formed on top of the strained silicon carbide channel layer. A gate insulation layer is formed on top of the silicon layer and strained silicon carbide channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal. Thus, standard materials for the spacer, such as silicon oxide or silicon nitride are not preferred for this application, because they tend to be transparent to the laser beam emissions.

Flash memory erase speed by fluorine implant or fluorination

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.

Strained silicon heterostructures : materials and devices

Abstract: * Chapter 1: Introduction * Chapter 2: Strained Layer Epitaxy * Chapter 3: Electronic Properties of Alloy Layers * Chapter 4: Gate Dielectrics on Strained Layers * Chapter 5: SiGe Heterojunction Bipolar Transistors * Chapter 6: Heterostructure Field Effect Transistors * Chapter 7: BICFET, RTD and Other Devices * Chapter 8: MODFETs * Chapter 9: Contact Metallization on Strained Layers * Chapter 10: Si/SiGe Optoelectronics

Low temperature formation of backside ohmic contacts for vertical devices

Abstract: A method for forming an ohmic contact to silicon carbide for a semiconductor device comprises implanting impurity atoms into a surface of a silicon carbide substrate thereby forming a layer on the silicon carbide substrate having an increased concentration of impurity atoms, annealing the implanted silicon carbide substrate, and depositing a layer of metal on the implanted surface of the silicon carbide. The metal forms an ohmic contact “as deposited” on the silicon carbide substrate without the need for a post-deposition anneal step.

Ultra small size vertical MOSFET device and method for the manufacture thereof

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source contact, a drain contact and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.

Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4

Abstract: A method of fabricating a semiconductor device having a gate structure comprising SiO2 and Si3N4 that exhibits reduced hydrogen diffusion during low temperature chemical vapor deposition of silicon nitride. In the method, a silicon dioxide (SiO2) layer is deposited on a wafer after a gate structure is fabricated. A barrier layer is formed on the silicon dioxide (SiO2) layer. Then a silicon nitride layer is formed over it by low temperature chemical vapor deposition. The barrier layer reduces, and may even altogether prevent, diffusion of the hydrogen absorbed by the silicon nitride layer into the gate oxide and channel during the low temperature chemical vapor deposition of silicon nitride.

Semiconductor thin film, semiconductor device and manufacturing method thereof

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of silicon film to a crystalline silicon film. Then, perform a second heat treatment in the halogen atmosphere forming on the crystalline silicon film a thermal oxide film containing halogen, whereby the crystalline silicon film alters to a mono-domain region.

Method of crystallizing a silicon thin film and semiconductor device fabricated thereby

Abstract: The present invention relates to a method of crystallizing an amorphous silicon thin film by thermal annealing the amorphous silicon thin film vapor deposited on a substrate in order to form a polycrystalline silicon thin film, and a semiconductor device fabricated by the method. According to the present invention, it is constructed such that a light-absorbing layer having absorbance of light much higher than that of the substrate or the amorphous silicon thin film is formed around the amorphous silicon thin film and is heated by a lamp when crystallizing the amorphous silicon thin film vapor deposited on the substrate by rapid annealing. Therefore, the temperature of the amorphous silicon thin film can be raised while restraining the increase in temperature of the substrate to the utmost. Accordingly, the amorphous silicon thin film can be crystallized without deformation of the substrate.

Properties of electronic traps at silicon/1-octadecene interfaces

Abstract: Silicon surfaces with (111) orientation were hydrogenated in NH4F solution. Alkyl chain monolayers were self-assembled on the hydrogen-terminated silicon (Si–H) surface by the free-radical reaction of 1-octadecene and SiH, activated by ultraviolet (253.7 nm) illumination. Comprehensive electrical characterization of the metal/1-octadecene/silicon structures yielded experimental data on the (silicon–monolayer) interface trap parameters. The admittance data indicated the realization of a true silicon/organic-monolayer interface. The interface trap density obtained, for p-type silicon, was 1.7–3.0×1011/cm2 V over an energy range of 0.22–0.73 eV over the valence band edge. These interface trap densities can be considered remarkably low for a silicon interface formed around room temperature, and are an order of magnitude lower than what was obtained in the case of alkyl chain organic monolayers on naturally oxidized silicon surfaces. The interface trap density was found to be strongly influenced by the silicon...

Superior silicon carbide integrated circuits and method of fabricating

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices. Such devices are derived from a method for forming a silicon region on a silicon carbide substrate which comprises the steps of: providing a monocrystalline silicon carbide substrate; amorphizing at least one region of the substrate, preferably by subjecting at least a portion of a surface of the substrate to ion implantation to convert at least a portion of the substrate surface to amorphous silicon carbide producing a region of amorphous silicon carbide on a monocrystalline silicon carbide substrate; removing at least an effective amount of carbon from said amorphized region, preferably by subjecting at least a portion of the amorphous silicon carbide region to an etchant material which selectively removes carbon to produce a region of amorphous silicon on a monocrystalline silicon carbide substrate; and subjecting the monocrystalline substrate with at least a region of amorphous silicon to high temperature thermal anneal to produce a region of monocrystalline silicon on said monocrystalline silicon carbide substrate.

SiGe/SOI CMOS and method of making the same

Abstract: The present invention provides a method of fabricating a simple SiGe/SOI structure. In particular, the top silicon layer of a SOI is converted to Si1−xGex, by growing a SiGe epitaxial layer followed by relaxation annealing at a temperature between 550° C. to 1050° C. This temperature treatment relaxes the SiGe to convert the top silicon layer into a relaxed SiGe layer and eliminates defects in the SOI film. Accordingly, a very low defect density SiGe crystal is obtainable. The SiGe layer is capped with an epitaxial silicon layer. Because the silicon layer is grown onto the relaxed SiGe, the top silicon layer is a strained silicon layer. Therefore, higher electron and hole mobility are obtained. The buried oxide interface acts as a buffer for the SiGe relaxation. There is no requirement for a graded SiGe layer. As a result the defect density in this structure can be substantially lower than that of prior art structures.

Recrystallization method of polysilicon film in thin film transistor

Abstract: The present invention proposes a crystallization method of the poly-Si thin film in a thin film transistor. A substrate having an insulator layer is provided. An amorphous silicon layer or a micro-crystalline silicon layer having two thickness is first formed on the insulator layer. The region of thinner is defined as the channel region of the TFT, while the region of thicker can be defined as the source/drain regions of the TFT. Next, an excimer laser is used for crystallization. During the excimer laser irradiation, the amorphous silicon layer of thinner is completely melted, and the amorphous silicon layer of thicker is partially melted. The partially melted amorphous silicon layer is used as crystallization seeds. Through formation of the temperature gradient between the completely melted amorphous silicon layer and the partially melted amorphous silicon layer, longitudinal growth of silicon grains in the completely melted region will be performed to grow a poly-Si layer having good homogeneity and large grains.