Showing papers on "Transistor published in 1986"

Device electronics for integrated circuits

Abstract: Semiconductor Electronics. Silicon Technology. Metal--Semiconductor Contacts. pn Junctions. Currents in pn Junctions. Bipolar Transistors I: Basic Properties. Bipolar Transistors II: Limitations and Models. Properties of the Metal--Oxide--Silicon System. Mos Field--Effect Transistors I: Physical Effects and Models. Mos Field--Effect Transistors II: High--Field Effects. Answers to Selected Problems. Selected List of Symbols. Index.

Macromolecular electronic device: Field-effect transistor with a polythiophene thin film

Abstract: The first solid‐state field‐effect transistor has been fabricated utilizing a film of an organic macromolecule, polythiophene, as a semiconductor. The device characteristics have been optimized by controlling the doping levels of the polymer. The device is a normally off type and the source (drain) current can be modulated by a factor of 102–103 by varying the gate voltage. The carrier mobility and the transconductance have also been determined to be ∼10−5 cm2/V s and 3 nS, respectively, by means of electrical measurements.

Characterisation and modeling of mismatch in MOS transistors for precision analog design

Abstract: A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.

Simple technique for separating the effects of interface traps and trapped‐oxide charge in metal‐oxide‐semiconductor transistors

Abstract: A new technique is presented for separating the threshold‐voltage shift of a metal‐oxide‐semiconductor transistor into shifts due to interface traps and trapped‐oxide charge. This technique is applied to threshold‐voltage shifts on an n‐channel transistor that result from ionizing radiation.

Integrated semiconductor magnetic field sensors

Abstract: A magnetic field sensor is an entrance transducer that converts a magnetic field into an electronic signal. Semiconductor magnetic field sensors exploit the galvanomagnetic effects due to the Lorentz force on charge carriers. Integrated semiconductor, notably silicon, magnetic field sensors, are manufactured using integrated circuit technologies. Integrated sensors are being increasingly developed for a variety of applications in view of the advantage offered by the integration of the magnetic field sensitive element together with support and signal processing circuitry on the same semiconductor chip. The ultimate goal is to develop a broad range of inexpensive batch-fabricated high-performance sensors interfaced with the rapidly proliferating microprocessor. This review aims at the recent progress in integrated silicon magnetic devices such as integrated Hall plates, magnetic field-effect transistors, vertical and lateral bipolar magnetotransistors, magnetodiodes, and current-domain magnetometers. The current development of integrated magnetic field sensors based on III-V semiconductors is described as well. Bulk Hall-effect devices are also reviewed and serve to define terms of performance reference. Magnetic device modeling and the incorporation of magnetic devices into an integrated circuit offering in situ amplification and compensation of offset and temperature effects are further topics of this paper. Silicon will continue to be aggressively exploited in a variety of magnetic (and other) sensor applications, complementary to its traditional role as integrated circuit material.

Subthreshold slope of thin-film SOI MOSFET's

Abstract: Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel For comparison, the subthreshold slope of transistors made in thicker films is also reported

The delta-doped field-effect transistor (δFET)

Abstract: A field-effect transistor (FET) using a two-dimensional electron gas (2DEG) as an electron channel is fabricated from GaAs grown by molecular-beam epitaxy. The doping profile of the field-effect transistor is described by the Dirac delta (δ) function. The subband structure of δ-doped GaAs is calculated. The characteristics of the δFET are a high concentration of the 2DEG, a high breakdown voltage of the Schottky contact, a narrow distance of the 2DEG from the gate, and a high transconductance. These properties are analyzed. Preliminary results for the extrinsic transconductance and for the transit frequency are obtained from δFET's having nonoptimized structures.

The n-channel SiGe/Si modulation-doped field-effect transistor

Abstract: At the heterointerface of Si 1-x Ge x /Si the existence of two-dimensional carrier gas has recently been demonstrated. The electrons are confined inside the large-gap material Si. We report the first fabrication of n-channel modulation-doped SiGe/Si hetero field-effect transistors by use of molecular-beam epitaxial growth. Though neither layer sequence nor parasitic resistances were optimized, these first transistors exhibit an extrinsic transconductance of 40 mS/mm for a gate length of 1.6 µm. This value is higher than that of conventional Si MESFET's of comparable carrier concentration. Technological processing steps and device evaluation are described.

A CMOS Four-Quadrant Analog Multiplier

Abstract: A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

Output circuit having transistor monitor for matching output impedance to load impedance

Abstract: An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line. Transmission with transmitting and receiving ends having a well-defined transmission waveform is obtained, thereby making possible high-speed signal transmission between LSI chips.

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

Abstract: The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.

Metastable defects in amorphous-silicon thin-film transistors.

Abstract: When a positive gate voltage is applied to an amorphous-silicon thin-film transistor, electrons become trapped in states close to the silicon-dielectric interface. This is studied by a new technique involving the transient discharge current produced under illumination. It is suggested that the behavior may involve metastable dangling bonds generated within the amorphous silicon as a consequence of the field-effect-induced increase in electron concentration. This constitutes an important new instability mechanism for amorphous-silicon thin-film transistors.

Quantum-well resonant tunneling bipolar transistor operating at room temperature

Abstract: The first resonant tunneling bipolar transistor (RBT) is reported. The AlGaAs/GaAs wide-gap emitter device, grown by molecular beam epitaxy (MBE), contains a GaAs quantum well and two AlAs barriers between the emitter and the collector. In the common emitter configuration, when the base current exceeds a threshold value, a large drop in the collector current (corresponding to a quenching of the current gain β) is observed at room temperature, along with a pronounced negative conductance as a function of the collector-emitter voltage. These striking characteristics are caused by the quenching of resonant tunneling through the double barrier as the conduction band edge in the emitter is raised above the bottom of the first quantized subband of the well. Single-frequency oscillations are observed at 300 K. The inherent negative transconductance of these new functional devices is extremely valuable for many logic and signal processing applications.

Semiconductor device with protective means against overheating

Abstract: A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

Static and dynamic analysis of amorphous-silicon field-effect transistors

Abstract: Analytical expressions have been developed for the analysis of static and dynamic behaviour of hydrogenated-amorphous-silicon based field-effect transistors. The current/voltage, capacitances and transcapacitances/voltage characteristics are related to the material parameters. The characteristic temperature, Tc, of the exponential band-tail states distribution is shown to influence strongly their shape and magnitude. An exact integration of the potential in the structure has allowed us to give expressions for the source and drain resistances. Finally, we present an equivalent circuit of a-Si:H TFT which can be employed in circuit simulation for the optimisation of integrated circuits.

Method of making a heterojunction bipolar transistor with SIPOS

Abstract: A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Method of making a customized semiconductor integrated device

Abstract: A method of fabricating a plurality of electronic circuits with transistors in schematic form in a customizable semiconductor integrated device, such as a base array, is disclosed. The base array has a plurality of chains of continuously electrically connected transistors, all of the same type, with the drain of a transistor connected to the source of an adjacent transistor. The schematic transistors are grouped by diffusion line tracing to form a plurality of groups. Each group of schematic transistors is assigned to physical transistors in the base array. The cost function associated with each group of physical transistors is calculated. The total cost function is optimized by changing the assignment of one or more groups of the schematic transistors to the physical transistors. The electrical interconnection from one group of physical transistors to another group of physical transistors is routed to form the physical layout of the circuit. Isolation transistors are also provided to isolate physical layouts of the circuit from one another or to provide isolation between groups of physical transistors where isolation is needed. The gate of each isolation transistors is connected to a voltage source thereby isolating the physical layouts of the circuits.

Fast switching lateral insulated gate transistor

Abstract: The switching speed of the Lateral Insulated Gate Transistor (LIGT) is slow compared to that of similar LDMOS power devices. The LIGT described in this paper, however, is designed to have both fast, switching and high current conduction. The speed improvement is achieved by using a modified LIGT structure, where an additional n+region is added to the p+injector. The turn-off time of this modified LIGT is less than 450 nanoseconds, while turn-on is under 100 nanoseconds. Computer simulation is used to understand the role of the shorted anode in improving the switching speed of the LIGT. A comparison with fabricated devices is shown to be in good qualitative agreement.

Slew-rate limited output driver having reduced switching noise

Abstract: An output circuit device according to the present invention comprises first circuit means (1) having a first type MOS transistor and a second type MOS transistor connected in parallel to each other, second circuit means (3) having at least a first type MOS transistor and a second type MOS transistor connected in parallel to each other, and a load capacitor means (13) connected between the output terminal and the ground potential for charging and discharging electric charge of an output signal. The source of said first type MOS transistor is connected to a first power supply and the source of said second type MOS transistor being connected to a second power supply. The second circuit means is connected between the output of said first circuit means and an output terminal. The source of the first type MOS transistor in the second circuit means is connected to the first power supply. The source of the second type MOS transistor is connected to the second power supply. The first and second type MOS transistors have a first threshold voltage level. Thereby, undershoot and overshoot phenomena are suppressed when the output potential of the first and second type MOS transistors in the second circuit means reaches the threshold voltage level.

Control of a natural permeable CoSi2 base transistor

Abstract: We report results on the fabrication of a natural permeable base transistor in a Si/CoSi2/Si heterostructure using molecular beam epitaxy (MBE). No photolithography is required, the transistor action being controlled by MBE growth conditions through the density and size of natural openings in the silicide base. The electrical characteristics of devices processed from such heterostructures are intimately related to the presence of these openings. Common base current gains in the range 0.01–0.95 have been observed and correlated with the size and density of the openings.

Thin film FET doped with diffusion inhibitor

Abstract: The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.

Semiconductor memory device

Abstract: A semiconductor memory device including at least one pair of memory cell arays having (1, 2) a plurality of word lines (W+ 101, 102, ...), a plurality of bit lines (BL-1, BL-1, BL-2, ...) and a plurality of memory cells (MC) disposed at the intersecting points of the word lines and the bit lines. A plurality of word line driving transistors (T(1), T(11)) are connected to the word lines and aligned at the inner edges of the pair of memory cell arrays. The pitch of a pair of word line driving gate circuits (D01, D02; D11, D12) is matched to the pitch of the two adjacent wordlines, and at least a pair of word lines driving gate circuits are arranged along the direction of the word lines between the pair of memory cell arrays. The outputs of the word line driving gate circuits are connected to the word line driving transistors at both sides of the word line driving gate circuits. A plurality of decoder lines (D1, D2, D3, D4) extend between the pair of word line driving gate circuits (D01, D11) and are connected to the input terminals of the word line driving gate circuits.

Realization of quaternary logic circuits by n-channel MOS devices

Abstract: A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.

Fabrication of double diffused metal oxide semiconductor transistor

Abstract: In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.

A novel submicron LDD transistor with inverse-T gate structure

Abstract: A novel submicron LDD transistor is demonstrated in which there is a thin extension of the gate polysilicon under the oxide sidewall-spacer giving the gate's cross section the appearance of an inverted letter T. The new inverse-T LDD (ITLDD) transistor features the self alignments of n-LDD and n+source-drain implants to the inside and outside edge, respectively, of the IT gate structure. Optimum n-LDD length for reducing the electric field in the channel region can be achieved by controlling the width of the oxide sidewall-spacer abutting the ledge of the IT-gate in a similar manner to a conventional LDD transistor. However, the "spacer-induced degradations" existing in a conventional LDD transistor are eliminated as a result of the self-aligned n+-to-gate feature in ITLDD. This allows the use of low n-LDD dose for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicron ITLDD transistor with improved transconductance and reliability has been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.

Optical Clock Distribution To Silicon Chips

Abstract: Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce the leak current of a high withstand voltage element as well as to prevent the generation of a latch-up phenomenon in a low withstand voltage element region by a method wherein a film which transmits no oxygen is covered on a low withstand voltage element region, a heat treatment is performed thereon, and then another heat treatment is performed after said film has been exfoliated. CONSTITUTION:Impurities are ion-implanted on the surface of an Si substrate 31 for the purpose of forming an N-well 32 to be used for an MOS. Then, a film 35 is provided on the substrate surface of a low withstand voltage element region 37, and the diffusion of oxygen in the substrate 31 located directly below the film 35 is prevented. On the other hand, a nitriding preventing film 36 is provided on the substrate surface of a high withstand voltage element region 38. A heat treatment is performed under the above-mentioned state. As a result, a deep defectless layer 34 is formed in the substrate 31 located directly below the region 38, and subsequently films 35 and 36 are exfoliated. Then, a new nitriding-preventing film 39 is provided, a heat treatment is performed, and a defectless layer 40 is formed. Subsequently, a C-MOS transistor (TR) is formed in the region 37, and a high withstand voltage MOSTR is formed in the region 38. As a result, the leak current on the P-N junction of the high withstand voltage element can be reduced, thereby enabling to prevent the generation of latchup phenomenon when the C-MOS TR is formed on the region 37.

Thin film memory matrix using amorphous and high resistive layers

Abstract: Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Process for making a buried conductor by fusing two wafers

Abstract: A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched. A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming a compositional emitter, and with an n-semimetal boundary. The sink transistor of the guest is made with the wafer substrate forming the emitter, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming the compositional collector. The guest substrate is terminated with an n-semimetal boundary. A buried conductor contacts the collector of the host transistor and the emitter of the guest transistor.