Showing papers on "VHDL published in 1997"

VHDL: Analysis and Modeling of Digital Systems

Abstract: From the Publisher: Here's the new second edition of the authoritative reference engineers need to guide them through the use of VHDL hardware description language in the analysis, simulation, and modeling of complicated microelectronic circuits. You'll find extensive new material to bring the guide fully up to date with the new VHDL93 standard, including new chapters on design flow, interfacing, modeling, and timing. Extensive appendixes, including ones on logic synthesis and CPU description styles, provide up-to-date information on the use of VHDL in design. The number and depth of its relevant and practical examples and problems is what sets this edition apart from other VHDL texts.

Piecewise linear approximation applied to nonlinear function of a neural network

Abstract: An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses a simple digital gate design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. The comparison of this technique with two other sigmoidal approximation techniques for digital circuits is presented and the results show that the fast and compact digital circuit proposed produces the closest approximation to the sigmoid function. The hardware implementation of PLAN has been verified by a VHDL simulation with Mentor Graphics running under the UNIX operating system.

VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions

Abstract: A new technique for reliability evaluation of digital systems will be presented by demonstrating the functionality and usage of the simulation based fault injector VERIFY (VHDL-based Evaluation of Reliability by Injecting Faults efficientlY) This software tool introduces a new way for describing the behavior of hardware components in case of faults by extending the VHDL language with fault injection signals together with their rate of occurrence The accuracy of the results is obtained by using the same VHDL-models which have been developed during conventional phases of hardware design For demonstrating the capabilities of VERIFY, a VHDL-model of a simple 32-bit processor (DP32) will be used as an example to illustrate the several steps of reliability evaluation

An efficient implementation of reactivity for modeling hardware in the scenic design environment

Abstract: Reactivity is one of the key features of hardwaredescription languages. We present an efficient implementationof reactivity in the Scenic framework that allows the systemdesigner to model hardware blocks. Scenic allows the designerto use C++ to model mixed hardware-software systems witha C++ compiler and a small library and without the need ofa complex event-driven run-time kernel often found embeddedin hardware description languages (HDL) such as VHDL andVerilog. Moreover, Scenic hardware descriptions can be easilymapped to HDL and synthesized into hardware implementationsusing commercially available tools.In this paper we present Scenic's implementation of concurrency(signals and processes) and reactivity (waiting andwatching). When C++ is used as an HDL, context-switchingoverhead can become a significant performance issue duringsimulation. We introduce the notion of delayed expressionobjects, orlambdas, to reduce context-switching. Examplesand experimental results are presented to show the utility andsimulation efficiency using the Scenic framework.

Testability analysis and ATPG on behavioral RT-level VHDL

Abstract: This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.

Digital Systems Design and Prototyping Using Field Programmable Logic

Abstract: Field-programmable logic has been available for a number of years. The role of Field-Programmable Logic Devices (FPLDs) has evolved from simply implementing the system `glue-logic' to the ability to implement very complex system functions, such as microprocessors and microcomputers. The speed with which these devices can be programmed makes them ideal for prototyping. Low production cost makes them competitive for small to medium volume productions. These devices make possible new sophisticated applications, and bring up new hardware/software trade-offs and diminish the traditional hardware/software demarcation line. Advanced design tools are being developed for automatic compilation of complex designs and routings to custom circuits. Digital Systems Design and Prototyping Using Field Programmable Logic covers the subjects of digital systems design and (FPLDs), combining them into an entity useful for designers in the areas of digital systems and rapid system prototyping. It is also useful for the growing community of engineers and researchers dealing with the exciting field of FPLDs, reconfigurable and programmable logic. The authors' goal is to bring these topics to students studying digital system design, computer design, and related subjects in order to show them how very complex circuits can be implemented at the desk. Digital Systems Design and Prototyping Using Field Programmable Logic makes a pioneering effort to present rapid prototyping and generation of computer systems using FPLDs. From the Foreword: `This is a ground-breaking book that bridges the gap between digital design theory and practice. It provides a unifying terminology for describing FPLD technology. In addition to introducing the technology it also describes the design methodology and tools required to harness this technology. It introduces two hardware description languages (e.g. AHDL and VHDL). Design is best learned by practice and the book supports this notion with abundant case studies.' Daniel P. Siewiorek, Carnegie Mellon University CD-ROM INCLUDEDe Digital Systems Design and Prototyping Using Field Programmable Logic, First Edition includes a CD-ROM that contains Altera's MAX+PLUS II 7.21 Student Edition Programmable Logic Development Software. MAX+PLUS II is a fully integrated design environment that offers unmatched flexibility and performance. The intuitive graphical interface is complemented by complete and instantly accessible on-line documentation, which makes learning and using MAX+PLUS II quick and easy. The MAX+PLUS II version 7.21 Student Edition offers the following features: Operates on PCs running Windows 3.1, Windows 95 and Windows NT 3.51 and 4.0. Graphical and text-based design entry, including the Altera Hardware Description Language (AHDL) and VHDL. Design compilation for Product-term (MAX 7000S) and look-up table (FLEX 10K) device architectures. Design verification with full timing simulation.

System Synthesis with VHDL

Abstract: Preface. Part I: Preliminaries. 1. Introduction. 2. VHDL. 3. High-Level Synthesis. 4. System- Level Synthesis. 5. Optimization Heuristics. Part II: Transformational Approach. 6. Transformational Design Basics. 7. Synthesis of Advanced Features. 8. Hardware/Software Partitioning. Part III: Advanced Issues. 9. Test Synthesis. 10. Low-Power Synthesis. Bibliography. Index.

Digital Design and Modeling with VHDL and Synthesis

Abstract: From the Publisher: Combines VHDL and synthesis in an easy-to-follow step-by-step sequence. This approach addresses common mistakes and hard-to-understand concepts in a way that eases learning. Digital Design and Modeling with VHDL and Synthesis introduces VHDL with closely related practical design examples, simulation waveforms, and schematics so you can better understand their correspondence and relationship. This book is the result of the K.C. Chang's extensive experience in both design and teaching. Many of the design techniques and design considerations, illustrated throughout the chapters, are examples of real designs.

VHDL generation from hierarchical Petri net specifications of parallel controllers

Abstract: Parallel controllers can be best specified using a description with a formal support to validate structural and dynamic properties. Petri nets (PN) can provide an adequate means to model and to animate parallel systems based on the control and data path approach, in a hierarchically structured way. A set of tools was developed to allow formal validation of parallel controllers, based on hierarchical PN-based specifications and to automatically generate RT-level VHDL code. An example of a VLSI chip design, the transputer link adapter, shows the capabilities of this methodology and associated tools.

System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code

Abstract: A system and method for representing a system level RTL hardware design using an HDL independent RTL representation and translation into synthesizable RTL code. The present invention creates an object-oriented library which can be used to implement RTL hardware designs in terms of HDL independent objects. Instead of implementing multiple HDL instances of hardware modules, the invention enables software tool programmers to implement one HDL-independent instance of the hardware module. As a result, a programmer can focus his efforts on generating the functionality of the module and can be relieved from the time consuming task of generating the detailed syntax of multiple HDLs. The present invention also maintains synchronization across multiple HDLs so that a software designer can generate HDL code for any supported HDL, e.g., Verilog or VHDL, thus making software maintenance easier.

Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware

Abstract: Reed-Solomon (RS) error correction codes are being widely used in modern communication systems such as compact disk players or satellite communication links. RS codes rely on arithmetic in finite, or Galois fields. The specific field GF(2/sup 8/) is of central importance for many practical systems. The most costly, and thus most critical, elementary operations in RS decoders are multiplication and inversion in Galois fields. Although there have been considerable efforts in the area of Galois field arithmetic architectures, there appears to be very little reported work for Galois field arithmetic for reconfigurable hardware. This contribution provides a systematic comparison of two promising arithmetic architecture classes. The first one is based on a standard base representation, and the second one is based on composite fields. For both classes a multiplier and an inverter for GF(2/sup 8/) are described and theoretical gate counts are provided. Using a design entry based on a VHDL description, each architecture is mapped to a popular FPGA and EPLD device. For each mapping an area and a speed optimization was performed. Absolute values with respect to logic cell counts and critical path simulations are provided. The results show that the composite field architectures can have great advantages on both types of reconfigurable platforms. In particular it is found that composite field multipliers can be more than twice as fast as polynomial base multipliers on FPGAs.

A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Abstract: Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates. The area and timing results of the hardware implementation are presented and compared with a conventional loop iteration technique (also described in this paper). The CRC-32 polynomial, commonly used for most computer network protocol standards, was chosen to implement the algorithm.

Automated field-programmable compute accelerator design using partial evaluation

Abstract: This paper describes a compiler that generates both hardware and controlling software for field-programmable compute accelerators. By analyzing a source program together with part of its input, the compiler generates VHDL descriptions of functional units that are mapped on a set of FPGA chips and an optimized sequence of control constructions that run on the customized machine. The primary technique employed in the compiler is partial evaluation, which is used to transform an application program together with part of its input into an optimized program. Further phases in the compiler identify pieces of the program that can be realized in hardware and schedule computations to execute on the resulting hardware. Finally, a set of specialized functional units generated by the compiler for a timing simulation program is used to demonstrate the approach.

The T-Ruby Design System

Abstract: This paper describes the T-Ruby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctness-preserving transformations based on proved equivalences between relations, together with the addition of constraints. A class of implementable relations is defined. The tool enables such relations to be simulated or translated into a circuit description in VHDL. The design process is illustrated by the derivation of a circuit for 2-dimensional convolution.

VHDL 1076.1: analog and mixed-signal extensions to VHDL

Abstract: This presentation provides an overview of the 1076.1 effort to extend the well established VHDL language to support the description and simulation of continuous and mixed continuous/discrete systems. It begins with a brief history of the effort. That is followed by an overview of the foundations: the design objectives, the base VHDL 1076 language, and the applicable mathematical theory. The body of the presentation describes the elements of the extended language. Each language element is described in the context of the 1076.1 language architecture and illustrated by a brief example. The presentation ends with selected examples illustrating the use of the language for analog and mixed-signal applications.

A parallel/serial trade-off methodology for look-up table based decoders

Abstract: A methodology for architecture exploration of look-up tablebased decoders is presented. For the degree of parallel processinga trade-off can be made by exploring system leveland register transfer level models. Executable specifications(pure functional software models, VHDL behavior models)are used to analyze the performance of different architectures.Hardware cost (area) and feasibility (timing) aredetermined by synthesis of RTL models. These models aregenerated directly out of the specification to avoid errorsdue to manual transformations and to reduce overall designtime. Generator-based reuse modeling and hardware costestimation is demonstrated using a decoder for MPEG variablelength codes (VLC).

Hardware/software co-simulation in a VHDL-based test bench approach

Abstract: Novel test bench techniques are required to cope with afunctional test complexity which is predicted to grow muchmore strongly than design complexity. Our test benchapproach attacks this complexity by using a stronghierarchical architecture, application domain-independentsynchronization, reusable modules, and easy incrementalextendability based on table-driven techniques. In addition,the integration of VHDL/C co-simulation under the controlof the test bench makes it possible to use the hardware modelfor software testing and vice versa and thus enables extremereductions in test bench coding. The efficiency of our testbench has already been demonstrated in several industrialprojects, among them a four-ASIC ATM board with oneembedded core and one external micro controller.

Hierarchical VHDL libraries for DSP ASIC design

Abstract: Methods are presented for the rapid design of DSP ASICs based on the use of hierarchical VHDL libraries. These are portable across many silicon foundries and allow complex DSP silicon systems to be developed in a fraction of the time normally required. Resulting designs are highly competitive with ones created using conventional methods. The approach is illustrated by its application to ADPCM codec and DCT cores.

Limes: a multiprocessor simulation environment for PC platforms

Abstract: This paper presents a multiprocessor simulation environment, developed with the aim to facilitate the researches of multiprocessor systems at the University of Belgrade. It comprises a simulation tool applicable for architecture studies of shared-address space multiprocessors, and a detailed model of bus-based cache coherent multiprocessor system. The environment executes on PC platforms and, while showing comparable performance with other tools of similar purpose, benefits from potential reusability of its realistic simulated models. The tool provides a simple general interface that allows for the hardware lying underneath the simulated processors to be modeled in a manner similar to the VHDL approach, but with far greater efficiency. The included model is easily extendible to other bus-based systems, and the basics of the design methodology are presented.

Analog and mixed-signal hardware description languages

Abstract: 1. Applicability of Discrete Event Hardware Description Languages to the Design and Documentation of Electronic Analog Systems A. Dewey. 2. VHDL 1076.1: Analog and Mixed-Signal Extensions to VHDL E. Christen, K. Bakalar. 3. Analog Extensions to Verilog R. Trihy. 4. OP3: A Behavioral Generic Model of Operational Amplifiers K.G. Ruan, I.E. Getreu. 5. Non-Linear State Space Averaged Modeling of a 3-State Digital Phase-Frequency Detector J. Chen. 6. Behavioural Modelling of Analogue Systems with Absynth V. Moser, et al. 7. VHDL-1076.1 Modeling Examples for Microsystem Simulation B. Romanowicz, et al. Index.

Object oriented extensions to VHDL, the LaMI proposal

Abstract: VHDL[14] is a language for describing digital hardware. It provides many attractive features and supports an efficient design methodology. However, there are certain limitations to the power of the language that can be addressed, at least partially, by Object Oriented Extensions. Several proposals were made to extend VHDL and add mechanisms from the object oriented domain. In this paper we describe the study, carried out by the LaMI laboratory, of another approach to Object Oriented extensions to VHDL in view of a future revision of the language. Related works will be reviewed and the motivations for this proposal will be introduced and illustrated through examples.

SUAVE: painless extension for an object-oriented VHDL

Abstract: The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. In addition to supporting object-orientation, these extended mechanisms improve the expressiveness of VHDL across the modeling spectrum, from high-level to gate-level. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. The paper outlines the SUAVE extensions and illustrates their use through some examples. The mechanisms and examples are readily understood as incremental extensions to current modeling practices, hence "painless extension".

RSFQ microprocessor: new design approaches

Abstract: We present a revised version of our previous RSFQ (Rapid Single Flux Quantum) microprocessor architecture and discuss approaches that we are using in the design of its functional units. In particular, the data processing pipeline built of D/sup 2/ cells, a 16-bit pipelined register block and an all-RSFQ self-reset decoder suitable for pipelined implementation are described in detail. Methods of VHDL description and verification of RSFQ circuitry are also discussed.

Register transfer level (RTL) based scan insertion for integrated circuit design processes

Abstract: A design-level description of a circuit is processed to incorporate testability functions in the form of scan chains. The design-level description may be a Register Transfer Level (RTL) description in accordance with the VHDL standard. The design-level description includes processes describing operations of the circuit. The processes are analyzed to identify data carriers in the design-level description which correspond to flip-flops or other specified elements in the circuit. The specified elements are organized into scan chains, which are then allocated to appropriate modules of the circuit. Scan ordering and scan insertion operations are performed separately on each of the modules. The scan ordering operation is based on functional relationships between the data carriers in the processes associated with the modules. The functional relationships can include both word-level and bit-level dependencies. The scan insertion operation involves inserting scan assignment statements into the processes. The modified design-level descriptions of the modules are separately synthesized to generate gate-level descriptions of the circuit modules, such that the overall circuit includes the appropriate scan chains.

A two-level approach to automated conformance testing of VHDL designs

Abstract: For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential.

Functional verification of the CMOS S/390 parallel enterprise server G4 system

Abstract: Verification of the S/390® Parallel Enterprise Server G4 processor and level 2 cache (L2) chips was performed using a different approach than previously. This paper describes the methods employed by our functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure and time-to-market constraints. Verification proceeded at four basic levels defined by the breadth of logic being tested. The lowest level, designer macro verification, contained a single designer's hardware description language (in VHDL). Unit-level verification consisted of a logical portion of function that generally contained four or five designers' logic. The third level of verification was the chip level, in which the processor or L2 chips were individually tested. Finally, system-level verification was performed on symmetric multiprocessor (SMP) configurations that included bus-switching network (BSN) chips and I/O connection chips, designated as memory bus adaptors (MBAs), along with multiple copies of the processor and L2 chips.

A Behavioural VHDL Synthesis System using Data Path Optimisation

Abstract: MOODS (Multiple Objective Optimisation in Data and control path synthesis) is a synthesis system which provides the ability to automatically optimise a design from a behavioural to a structural VHDL description. This thesis details two sets of enhancements made to the original system to improve the overall quality of the final hardware implementations obtained, and expand the range of the accepted VHDL subset. Whereas the original MOODS considered each functional unit in the target module library to be a purely combinational logic block, the ?expanded modules? developed for this project provide a means of implementing sequential multi-cycle modules. These modules are defined as technology-independent templates, which are inline expanded into the internal design structure during synthesis. This enables inter-module optimisation to occur at the sub-module level, thus affording greater opportunities for unit sharing and module binding. The templates also facilitate the development of specialised interface modules. These enable the use of fixed timing I/O protocols for external interfacing, while maintaining maximum scheduling flexibility within the body of the behaviour. The second set of enhancements includes an improved implementation of behavioural VHDL as input to the system. This expands the previously limited subset to include such elements as signals, wait statements, concurrent processes, and functions and procedures. These are implemented according to the IEEE standard thereby preserving the computational effects of the VHDL simulation model. The final section of work involves the development and construction of an FPGA-based real-time audio-band spectrum analyser, synthesised within the MOODS environment. This design process provides valuable insights into the strengths and weaknesses of both MOODS and behavioural synthesis in general, serving as a firm foundation to guide future development of the system.

FPGA implementation of high performance FIR filters

Abstract: This paper presents the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. Various well known multiplier architectures are compared and an appropriate structure for FPGA implementation is identified. The high data throughput required to accommodate the input sample values is achieved using an interleaved memory structure. To provide flexibility, a generic VHDL filter model has been developed which allows the automatic synthesis from specification down to FPGA realisation. The model operates on 2's complement numbers and is characterised by three user defined parameters: number of filter taps, signal and coefficient wordlengths. To demonstrate the design process, the implementation of a 64 tap linear phase filter with 60 dB attenuation at 0.28 fs, 12 dB attenuation at 0.25 fs and a passband ripple of /spl plusmn/0.01 dB up to 0.22 fs is included. The filter with 10 bit signal and 8 bit coefficient wordlength has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4 MHz.

Coloured Petri net model of application specific logic controller programs

Abstract: A new class of Petri nets, called coloured control interpreted Petri nets (CCIPN), is introduced. The advantages of CCIPN modelling for specification of logic controller programs are shown. We combine the coloured interpreted Petri nets (treated as an object) with the object-oriented controlled part. Apart from several papers we do not specify the coloured tokens as dynamically evaluated composite objects, but as a part of the object. The net is constructed from the simpler objects that are related with VHDL entities from the user-defined library. The formal objects that describe the controlled part (electro-mechanical system) are related with the coloured tokens in the Petri net. The linked coloured Petri nets that describe the objects are combined with a coloured Petri net specifying the logic controller. They are refined and combined into a complete Petri net system (total model). It may be simulated, verified and synthesized in a user-friendly VHDL environment, collaborating with our experimental design tools. Our technique is illustrated by presenting a solution to the popular "tank filling" problem. The proposed methods are especially useful in designing of industrial application specific logic controller with FPLD (FPGA and CPLD).

Modeling VHDL specifications as consistent EFSMs

Abstract: The dramatic increase in the complexity of digital systems has led to the use of formal description languages such as VHDL. This paper presents the preliminary results on properties of VHDL specifications that allow for automatic test generation without the exponential growth. In general, VHDL specifications can be modeled as extended finite machines (EFSMs). A class of EFSMs, called consistent EFSMs, allows for the finite state machines (FSM) based test generation techniques to be directly applied to VHDL specifications. An algorithm to identify the consistent EFMSs is introduced.