Showing papers on "Wafer published in 2007"

Making graphene visible

Abstract: Microfabrication of graphene devices used in many experimental studies currently relies on the fact that graphene crystallites can be visualized using optical microscopy if prepared on top of silicon wafers with a certain thickness of silicon dioxide. We study graphene's visibility and show that it depends strongly on both thickness of silicon dioxide and light wavelength. We have found that by using monochromatic illumination, graphene can be isolated for any silicon dioxide thickness, albeit 300 nm (the current standard) and, especially, approx. 100 nm are most suitable for its visual detection. By using a Fresnel-law-based model, we quantitatively describe the experimental data without any fitting parameters.

Two-dimensional silicon photonic crystal based biosensing platform for protein detection.

Abstract: We theoretically and experimentally demonstrate an ultrasensitive two-dimensional photonic crystal microcavity biosensor. The device is fabricated on a silicon-on-insulator wafer and operates near its resonance at 1.58 μm. Coating the sensor internal surface with proteins of different sizes produces a different amount of resonance redshift. The present device can detect a molecule monolayer with a total mass as small as 2.5 fg. The device performance is verified by measuring the redshift corresponding to the binding of glutaraldehyde and bovine serum albumin (BSA). The experimental results are in good agreement with theory and with ellipsometric measurements performed on a flat oxidized silicon wafer surface.

Method and apparatus for processing a wafer

Abstract: A method of a single wafer wet/dry cleaning apparatus comprising: a transfer chamber having a wafer handler contained therein; a first single wafer wet cleaning chamber directly coupled to the transfer chamber; and a first single wafer ashing chamber directly coupled to the transfer chamber.

Graphene transistors fabricated via transfer-printing in device active-areas on large wafer

Abstract: We demonstrate a method that uses the pillars on a stamp to cut and exfoliate graphene islands from a graphite and then uses transfer printing to place the islands from the stamp into the device active-areas on a substrate with a placement accuracy potentially in nanometers. The process can be repeated to cover all device active-areas over an entire wafer. We also report the transistors fabricated from the printed graphene. The transistors show a hole and electron mobility of 3735 and 795 cm2/V-s, respectively, and a maximum drive-current of 1.7 mA/μm (at VDS = 1 V), which are among the highest reported for room temperature. The effects of various transferring and fixing layers on sticking graphenes to a stamp and to a substrate, respectively, were also investigated.

Synthesis and characterization of atomically-thin graphite filmson a silicon carbide substrate,

Abstract: This paper reports the synthesis and detailed characterization of graphite thin films produced by thermal decomposition of the (0001) face of a 6H-SiC wafer, demonstrating the successful growth of single crystalline films down to approximately one graphene layer. The growth and characterization were carried out in ultrahigh vacuum (UHV) conditions. The growth process and sample quality were monitored by low-energy electron diffraction, and the thickness of the sample was determined by core level x-ray photoelectron spectroscopy. High-resolution angle-resolved photoemission spectroscopy shows constant energy map patterns, which are very sharp and fully momentum-resolved, but nonetheless not resolution limited. We discuss the implications of this observation in connection with scanning electron microscopy data, as well as with previous studies.

Top layers of metal for high performance IC's

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Wafer level stack structure for system-in-package and method thereof

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

Spatially resolved series resistance of silicon solar cells obtained from luminescence imaging

Abstract: The fast determination of the spatially resolved series resistance of silicon solar cells from luminescence images is demonstrated. Strong lateral variation of the series resistance determined from luminescence images taken on an industrial screen printed silicon solar cell is confirmed qualitatively by a Corescan measurement and quantitatively by comparison with the total series resistance obtained from the terminal characteristics of the cell. Compared to existing techniques that measure the spatially resolved series resistance, luminescence imaging has the advantage that it is nondestructive and orders of magnitude faster. © 2007 American Institute of Physics. DOI: 10.1063/1.2709630 The series resistance of silicon solar cells often exhibits strong lateral variations, particularly in industrial screen printed cells. Experimental techniques to quantify such variations include Corescan, 1 Cello, 2 and imaging techniques based on dark and illuminated infrared lock-in thermography LIT. 3,4 These techniques require data acquisition times between minutes and several hours per solar cell. Electroluminescence EL and photoluminescence PL imaging are very fast characterization tools for silicon solar cells and silicon wafers, with data acquisition times of a few seconds or less per sample. 5,6 Using EL images and PL images taken with external control of the voltage to measure lateral variations of the series resistance in silicon solar cells was proposed in Ref. 7. Some preliminary qualitative results were also reported. 7,8 Here, we demonstrate a quantitative determination of the series resistance and its lateral variation in a monocrystalline industrial screen printed silicon solar cell by luminescence imaging. Photoluminescence images are taken using an 815 nm/25 W laser that is expanded to illuminate the cell area of 12.512.5 cm 2 homogeneously with up to 0.67 Sun equivalent illumination intensity. A thermoelectrically cooled silicon charge coupled device camera is used to capture luminescence images. For the PL images with simultaneous current extraction, two arrays of ten spring loaded contact pins are used to contact the busbars of the cell homogeneously. A commercially available instrument is used for Corescan measurements; illuminated IV curves are measured with a calibrated industrial cell tester. In a simplified case, a solar cell is described as a twodimensional network of parallel nodes, with each node consisting of a series connection of a local resistor Rs,i and a diode. The value of R s,i is given as

Industrial Silicon Wafer Solar Cells

Abstract: In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

Towards electrically conductive, self-healing materials.

Abstract: A novel class of organometallic polymers comprising N-heterocyclic carbenes and transition metals was shown to have potential as an electrically conductive, self-healing material. These polymers were found to exhibit conductivities of the order of 10(-3) S cm-1 and showed structurally dynamic characteristics in the solid-state. Thin films of these materials were cast onto silicon wafers, then scored and imaged using a scanning electron microscopy (SEM). The scored films were subsequently healed via thermal treatment, which enabled the material to flow via a unique depolymerization process, as determined by SEM and surface profilometry. A method for incorporating these features into a device that exhibits electrically driven, self-healing functions is proposed.

Wafer level packaging to lidded chips

Abstract: Methods are provided for making a plurality of lidded microelectronic elements (112). In an exemplary embodiment, a lid wafer (11) is assembled with a device wafer (10). Desirably, the lid wafer (11) is severed into a plurality of lid elements (40) to remove portions (46) of the lid wafer (11) overlying contacts (18) at a front face (26) of the device wafer (10) adjacent to dicing lanes (19) of the device wafer (10). Thereafter, desirably, the device wafer (10) is severed along the dicing lanes (19) to provide a plurality of lidded microelectronic elements (112).

Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Interleaved spring probe tip designs are defined which allow multiple probe contacts on very small integrated circuit pads. The shapes of probe tips are preferably defined to control the depth of probe tip penetration between a probe spring and a pad or trace on an integrated circuit device. Improved protective coating techniques for spring probes are also disclosed, offering increased reliability and extended useful service lives for probe card assemblies.

Fabrication and testing of planar chalcogenide waveguide integrated microfluidic sensor

Abstract: We have fabricated and tested, to the best of our knowledge, the first microfluidic device monolithically integrated with planar chalcogenide glass waveguides on a silicon substrate. High-quality Ge(23)Sb(7)S(70) glass films have been deposited onto oxide coated silicon wafers using thermal evaporation, and high-index-contrast channel waveguides have been defined using SF(6) plasma etching. Microfluidic channel patterning in photocurable resin (SU8) and channel sealing by a polydimethylsiloxane (PDMS) cover completed the device fabrication. The chalcogenide waveguides yield a transmission loss of 2.3 dB/cm at 1550 nm. We show in this letter that using this device, N-methylaniline can be detected using its well-defined absorption fingerprint of the N-H bond near 1496 nm. Our measurements indicate linear response of the sensor to varying N-methylaniline concentrations. From our experiments, a sensitivity of this sensor down to a N-methylaniline concentration 0.7 vol. % is expected. Given the low-cost fabrication process used, and robust device configuration, our integration scheme provides a promising device platform for chemical sensing applications.

A MEMS-based Air Flow Sensor with a Free-standing Micro-cantilever Structure

Abstract: This paper presents a micro-scale air flow sensor based on a free-standingcantilever structure. In the fabrication process, MEMS techniques are used to deposit asilicon nitride layer on a silicon wafer. A platinum layer is deposited on the silicon nitridelayer to form a piezoresistor, and the resulting structure is then etched to create afreestanding micro-cantilever. When an air flow passes over the surface of the cantileverbeam, the beam deflects in the downward direction, resulting in a small variation in theresistance of the piezoelectric layer. The air flow velocity is determined by measuring thechange in resistance using an external LCR meter. The experimental results indicate that theflow sensor has a high sensitivity (0.0284 ω/ms-1), a high velocity measurement limit (45ms-1) and a rapid response time (0.53 s).

Method of manufacturing soi wafer

Abstract: PROBLEM TO BE SOLVED: To provide an SOI-wafer manufacturing method whereby a high-quality epitaxial layer can be grown on an SOI layer more surely than in conventional cases. SOLUTION: The SOI-wafer manufacturing method is the one wherein an SOI layer and an epitaxial layer are formed on an insulator by at least creating a substrate whereon the SOI layer is formed on the insulator, and by growing the epitaxial layer on the SOI layer. After at least creating the substrate wherein the SOI layer is formed on the insulator, and before growing the epitaxial layer, the substrate is subjected to an HF processing. Thereafter, the epitaxial layer is grown on the SOI layer. COPYRIGHT: (C)2008,JPO&INPIT

Inverse slope isolation and dual surface orientation integration

Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Casting Single Crystal Silicon: Novel Defect Profiles from BP Solar's Mono2 TM Wafers

Abstract: A novel crystal growth method has been developed for the production of ingots, bricks and wafers for solar cells. Monocrystallinity is achievable over large volumes with minimal dislocation incorporation. The resulting defect types, densities and interactions are described both microscopically for wafers and macroscopically for the ingot, looking closely at the impact of the defects on minority carrier lifetime. Solar cells of 156 cm2 size have been produced ranging up to 17% in efficiency using industrial screen print processes.

A polyoxometalate-assisted electrochemical method for silicon nanostructures preparation: from quantum dots to nanowires.

Abstract: Si quantum dots, nanoparticles, nanowires, and ordered Si complex micro-/nanostructures can be obtained directly from silicon wafer by a polyoxometalate-assisted electrochemical method.

Semiconductor device and manufacturing method thereof

Abstract: A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

Method of cleaning substrate processing chamber, storage medium, and substrate processing chamber

Abstract: A method of cleaning a substrate processing chamber that enables formation of an oxide film on a surface of a processing chamber inside component to be prevented. A substrate processing chamber 11 has therein a processing space S into which a wafer W is transferred and carries out reactive ion etching on the wafer W in the processing space S. The substrate processing chamber 11 has an upper electrode plate 38 that comprises silicon and a lower surface of which is exposed to the processing space S. A dry cleaning is carried out on the upper electrode plate 38 using oxygen radicals produced from oxygen gas introduced into the processing space S. An oxide removal processing is carried out on the upper electrode plate 38 using fluorine ions and fluorine radicals produced from carbon tetrafluoride gas introduced into the processing space S.

Shrinkage ratio of PDMS and its alignment method for the wafer level process

Abstract: In the research area known as Lab-on-a-Chip, poly-dimethylsiloane (PDMS) is a popular material whose fabrication method is the replication of patterns by curing on a mold. Shrinkage of PDMS occurs when it is cured; this is a problem related to the alignment between the PDMS layer and the rigid substrate during the wafer-level processing. In this paper, the 2D shrinkage ratio of PDMS is measured experimentally for various curing conditions including the temperature, thickness, and mixing ratio of the curing agent and dilutant. In order to measure this, scale marks were patterned onto a 4 in. wafer and replicated onto a PDMS substrate. When the patterned Si wafer and PDMS substrate were aligned, the difference of each scale mark was observed. A cross-shaped groove was patterned with a scale mark as a align key for the easy alignment of substrates. For a general recipe, the measured shrinkage ratios of PDMS were 1.06, 1.52 and 1.94% for curing temperature of 65, 80 and 100°C, respectively. Considering the shrinkage ratio of PDMS, the design offset applied in a photomask is 1.07, 1.54 and 1.98% for curing temperature of 65, 80 and 100°C, respectively.

Techniques for low temperature ion implantation

Abstract: Techniques for low-temperature ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a wafer support mechanism to hold a wafer during ion implantation and to facilitate movement of the wafer in at least one dimension. The apparatus may also comprise a cooling mechanism coupled to the wafer support mechanism. The cooling mechanism may comprise a refrigeration unit, a closed loop of rigid pipes to circulate at least one coolant from the refrigeration unit to the wafer support mechanism, and one or more rotary bearings to couple the rigid pipes to accommodate the movement of the wafer in the at least one dimension.

Cathode liner with wafer edge gas injection in a plasma reactor chamber

Abstract: The disclosure concerns a wafer support for use in a plasma reactor chamber, in which the wafer support has a wafer edge gas injector adjacent and surrounding the wafer edge.

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

Abstract: A unit including a semiconductor element, e.g., a chip-scale package (350, 1350) or an optical sensor unit (10) is fabricated. A semiconductor element (300) has semiconductive or conductive material (316) exposed at at least one of the front (302) and rear surfaces (114) and conductive features (310) exposed thereat which are insulated from the semiconductive or conductive material. By electrodeposition, an insulative layer (304) is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts (308) and a plurality of conductive traces (306) are formed overlying the electrodeposited insulative layer (304) which connect the conductive features (310) to the conductive contacts (308). An optical sensor unit (10) can be incorporated in a camera module (1030) having an optical element (1058) in registration with an imaging area (1026) of the semiconductor element (1000).

Method and apparatus for processing a micro sample

Abstract: An object of the invention is to realize a method and an apparatus for processing and observing a minute sample which can observe a section of a wafer in horizontal to vertical directions with high resolution, high accuracy and high throughput without splitting any wafer which is a sample. In an apparatus of the invention, there are included a focused ion beam optical system and an electron optical system in one vacuum container, and a minute sample containing a desired area of the sample is separated by forming processing with a charged particle beam, and there are included a manipulator for extracting the separated minute sample, and a manipulator controller for driving the manipulator independently of a wafer sample stage.

Wafer transfer apparatus, wafer transfer method and storage medium

Abstract: One sensor constituted of a light emission element and a light-receiving element is provided in a path through which a wafer is transferred. The sensor is positioned so that the wafer passes through an area between the light emission element and the light-receiving element. Coordinates of the center of the wafer are calculated based on encoder values obtained when the wafer starts passing through the sensor and when the wafer completes passing through the sensor, position data of wafer transfer means corresponding to the encoder value, and the diameter of the wafer; and thereby the amount of positional deviation of the center of the wafer from a reference position is calculated.

Method to fabricate an ESD resistant tunneling magnetoresistive read transducer

Abstract: A method to fabricate a tunneling magnetoresistive (TMR) read transducer is disclosed. An insulative layer is deposited on a wafer substrate, and a bottom lead is deposited over the insulative layer. A laminated TMR layer, having a plurality of laminates, is deposited over the bottom lead. A TMR sensor having a stripe height is defined in the TMR layer, and a parallel resistor and first and second shunt resistors are also defined in the TMR layer. A top lead is deposited over the TMR sensor. The parallel resistor is electrically connected to the bottom lead and to the top lead. The first shunt resistor is electrically connected to the bottom lead and the wafer substrate, and the second shunt resistor is electrically connected to the top lead and the wafer substrate.