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Anabela Veloso

Researcher at Katholieke Universiteit Leuven

Publications -  190
Citations -  2175

Anabela Veloso is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 22, co-authored 164 publications receiving 1794 citations.

Papers
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Journal ArticleDOI

Vertical GAAFETs for the Ultimate CMOS Scaling

TL;DR: It is demonstrated that FinFets fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption.
Proceedings ArticleDOI

Review of FINFET technology

TL;DR: Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FinFET devices.
Proceedings ArticleDOI

The Complementary FET (CFET) for CMOS scaling beyond N3

TL;DR: The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework and can eventually outperform the finFET device and meet the N3 targets in power and performance.
Journal ArticleDOI

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

TL;DR: In this article, individual traps are studied in n-channel SiO"2/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N).