Showing papers by "Chenming Hu published in 1995"

Electromigration and stress-induced voiding in fine Al and Al-alloy thin-filmed lines

Abstract: Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine Al and Al-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures. Aspects examined include effects due to line isolation (the absence of reservoirs at conductor ends), solute and precipitate phenomena, conductor critical (Blech) length, microstructure, film deposition conditions, and thermal processing subsequent to film deposition. Emphasis is on the isolated, submicron-wide, Al(Cu)-based thin-film interconnection lines of IBM VLSI logic and memory chips.

High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application

Abstract: Ultra-thin tunnel oxide can conduct very high current through oxide via direct tunneling, and charge-to-breakdown increases dramatically due to less oxide damage. These facts point to a possibility of using thin tunnel oxide in the floating-gate device structure for dynamic memory applications. We have chosen MONOS structure in this study due to its immunity to pinhole-induced leakage and back-tunneling. The memory device exhibits fast WRITE/ERASE speed, high-endurance, long data retention and non-destructive READ. Further improvements are expected through process optimization. >

Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. The channel region is delta-doped or counter-doped which permits superior performance for high-end VSLI applications. A selective epitaxy on a counter-doped substrate can be used in a counter-doped device. Doped wells can be used in a bulk silicon substrate in forming the devices. Trenching can be used to isolate devices in the doped wells.

Formation of buried oxide in silicon using separation by plasma implantation of oxygen

Abstract: Plasma immersion ion implantation (PIII) is used to fabricate buried oxide layers in silicon. This ‘‘separation by plasma implantation of oxygen’’ (SPIMOX) technique can achieve a nominal oxygen atom dose of 2×1017 cm−2 in implantation time of about 3 min. SPIMOX is thus presented as a practical high‐throughput process for manufacturing silicon‐on‐insulator. In the SPIMOX samples prepared, three distinct modes of buried oxide microstructure formation are identified and related to the as‐implanted oxygen profiles. A first‐order model based on oxygen transport and oxide precipitation explains the formation mechanisms of these three types of SPIMOX layers.

SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films

Abstract: The effects of scaling MESA isolated (with sidewall reoxidation) SOI MOSFETs with respect to channel length, channel width, silicon film thickness and buried oxide thickness have been studied experimentally. Characteristics of narrow-width devices have a strong dependence on T/sub Si/. In devices with small T/sub Si/, narrow-width effect dominates over short channel effect. Thin buried oxide reduces self-heating and short channel effect, but results in a lower intrinsic current drive due to the effect of backside coupling. The trade-offs and limitations for scaling individual dimension in MESA isolated SOI MOSFETs are discussed.

An AC conductance technique for measuring self-heating in SOI MOSFET's

Abstract: In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices. >

Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits

Abstract: This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFET's with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFET's are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits. >

Characteristics of thermal stresses in Al(Cu) fine lines. II. Passivated line structures

Abstract: The effects of oxide confinement on the thermal stress and yield behavior of passivated Al(Cu) line structures have been studied as a function of linewidth to submicron dimensions using a bending‐beam technique. Principal stresses in the passivated line structures were deduced based on a micromechanical analysis of the curvatures of periodic line structures with lines oriented parallel and perpendicular to the beam direction. Results from the passivated Al(Cu) lines show that with decreasing linewidth, the magnitude of the principal stress components become higher until the line aspect ratio approaching one, then decreased. This behavior is consistent with theoretical predictions by analytical methods and finite element analyses. The stress behavior of the oxide passivation has also been deduced and its magnitude depended on the oxide morphology at the sidewall of the lines. Our result indicates a high level of stress in the sidewall which may cause crack formation during thermal cycling.

An electro-thermal model for metal-oxide-metal antifuses

Abstract: In this paper, a complete electro-thermal analysis is presented for the metal-oxide-metal antifuses. The application of the Wiedemann-Franz Law and the thin film effect on thermal and electrical conductivities of metal films were also discussed. Several key parameters for tungsten-oxide-tungsten antifuse were extracted. The reaction temperature between tungsten and oxide was estimated to be around 1300/spl deg/C. The core resistivity was found to be around 250 /spl mu//spl Omega//spl middot/cm. This model can be readily extended to the other metal-dielectric-metal systems. >

Method of forming an ESD and hot carrier resistant integrated circuit structure

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.

Ferroelectric nonvolatile dynamic random access memory device

Abstract: A dynamic random access memory cell is described which can operate either in volatile or nonvolatile mode. When operating in a volatile mode, the memory cell operates in the same manner as a conventional dynamic random access memory cell, that is, with charge being stored and discharged from a capacitor in the memory cell. Upon receipt of a suitable signal, however, the cell can be switched to a nonvolatile mode of operation. In this mode of operation, a pulse applied to the capacitor can place a ferroelectric film in the desired polarization state to represent the binary data. The ferroelectric film will hold its polarization state until the data is recalled and the cell reverts to operating in a volatile mode.

Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications

Abstract: With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the device performance in terms of current driving capability and switching speed. Recently MOSFET devices whose threshold voltages can be adapted during the transistor operation using the body effect have been proposed for low voltage and low power VLSI applications. In these devices, the threshold voltages are reduced by forward-biasing the body-to-source junction. In this paper we study the effect of the channel doping engineering on this threshold voltage reduction scheme.

Modeling electromigration lifetime under bidirectional current stress

Abstract: Electromigration reliability of interconnect under bidirectional current stress has been studied in a wide frequency range (mHz to 200 MHz). Experimental results show that the AC lifetime rises with the stress current frequency. The current density exponent and the activation energy of AC lifetime are found to be twice that of DC lifetime. Pure AC current stress failure at extremely high current density is believed to result from thermal migration of metal at hot/cold transition points. >

ESD and hot carrier resistant integrated circuit structure

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.

Circuit-level simulation of TDDB failure in digital CMOS circuits

Abstract: An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible. >

SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity

Abstract: A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits. >

Punchthrough transient voltage suppressor for low-voltage electronics

Abstract: Transient voltage suppressors for electronic circuits with power supply voltage of 33 V or lower are urgently needed but unavailable due to excessive leakage of low-voltage reversed p-n diodes We analyzed several candidate device structures by using two-dimensional device simulation Adopting the punchthrough mechanism in an n/sup +/p/sup +/p/sup -/n/sup +/ structure rather than the traditional avalanche mechanism in a p/sup +/n/sup +/ structure, we can achieve low standoff voltage with excellent performances in low leakage current, low capacitance, and low clamping voltage The new device appears to be satisfactory for protecting future electronic systems with power supply voltage at least down to 15 V >

Resonant-cavity enhanced (RCE) separate absorption and multiplication (SAM) avalanche photodetector (APD)

Abstract: We report a highly-efficient and wavelength-selective separate absorption and multiplication (SAM) avalanche photodiode (APD) with a thin (500 /spl Aring/) absorbing layer. The improved characteristics of the photodetector were obtained by placing the absorption and multiplication layers in a Fabry-Perot cavity. An external quantum efficiency of 77% was achieved with a spectral linewidth of less than 4 nm and an avalanche gain of more than 50. Noise measurements indicate that the impact ionization coefficient for electrons is larger than that for holes.

High endurance ultra-thin tunnel oxide for dynamic memory application

Abstract: Ultra-thin tunnel oxide can conduct very high current through oxide via direct tunneling; charge-to-breakdown increases dramatically due to less oxide damage. These facts point to a possibility of using ultra-thin tunnel oxide in the floating-gate device structure for dynamic-memory applications. We chose MONOS structure in this study due to its immunity to defect-induced leakage and back-tunneling. The memory device exhibits fast WRITE/ERASE speed, high endurance, long data retention and non-destructive READ. Further improvements are expected through process optimization.

Realistic worst-case SPICE file extraction using BSIM3

Abstract: In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these block are determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gates implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance.

Electromigration characteristics of TiN barrier layer material

Abstract: Electromigration reliability of TiN barrier layer itself has been studied. Our results show no electrically measurable electromigration. Resistance increase and open failure under high density current stress are apparently due to a purely thermally activated process with an activation energy of 1.5 eV. TiN resistance is projected to be stable for 10 years if the temperature of the hottest spot in TiN is kept below 408/spl deg/C, which together with electrical sheet resistance and thermal resistance determine the acceptable current density in TiN.

On-state reliability of amorphous silicon antifuses

Abstract: A unified model of the on-state reliability of a-Si antifuses is presented. This physical model accounts for both thermal activation and electromigration. Temperature at the conductive link is the temperature at which the antifuse is stressed and is controlled by the stress current, not the ambient. To ensure a 10 year lifetime, a-Si antifuses should be operated at a current value less than 60% of its programming current value.

Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor

Abstract: We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon‐on‐insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal‐over‐gate structure. Mix‐and‐match lithography, including the use of electron‐beam lithography for all critical levels, x‐ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to fa...

A novel SOI CBiCMOS compatible device structure for analog and mixed-mode circuits

Abstract: A novel SOI CBiCMOS compatible structure has been developed which can be operated as both an MOS and lateral bipolar transistor. During the MOS operation, the new structure provides a very effective body contact to eliminate the floating-body effects such as I-V kink, low breakdown voltage and the anomalous subthreshold characteristics. In the bipolar mode, the structure provides a very efficient base contact with low base resistance compared to most existing base contact schemes.

ESD reliability and protection schemes in SOI CMOS output buffers

Abstract: The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate. >

Dynamic threshold voltage mosfet for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact (20) and the device body (14) in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Statistical variation of NMOSFET hot-carrier lifetime and its impact on digital circuit reliability

Abstract: The statistical variation of NMOSFET hot-carrier lifetime is studied. The variation in lifetime among spatially separate dies is more significant than the variation within each die. Due to the statistical nature of device hot-carrier lifetime, hot-carrier induced circuit delay degradation in critical paths is a statistical distribution rather than a deterministic parameter. A statistical hot-carrier simulator has been developed to predict the impact that statistical variation of device hot-carrier lifetime has on circuit reliability.

Punchthrough transient voltage suppressor for EOS/ESD protection of low-voltage IC's

Abstract: A silicon transient voltage suppresser (TVS) is presented for off-chip EOS/ESD protection of ICs with supply voltages ranging from 3.3 V down to 1.5 V. The np/sup +/p/sup -/n four-layer TVS operates in punchthrough mode instead of the avalanche mode as in conventional TVS diodes. Performance was investigated by device simulator TMA-MEDICI for several device structure options for ultra-low-voltage EOS/ESD protection.