Showing papers by "Chenming Hu published in 2011"

Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation

Abstract: A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET operation, called the “antiferroelectric mode” is proposed, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the on-current in exchange for a nominal hysteresis. Design considerations for different device parameters (FE thickness, EOT, source/drain overlap & gate length) are explored. It is suggested that relative improvement in device performance due to FE negative capacitance becomes more significant in very short channel length devices because of the increased drain-to-channel coupling.

Ultrathin body InAs tunneling field-effect transistors on Si substrates

Abstract: An ultrathin body InAs tunneling field-effect transistor on Si substrate is demonstrated by using an epitaxial layer transfer technique. A postgrowth, zinc surface doping approach is used for the formation of a p+ source contact which minimizes lattice damage to the ultrathin body InAs compared to ion implantation. The transistor exhibits gated negative differential resistance behavior under forward bias, confirming the tunneling operation of the device. In this device architecture, the ON current is dominated by vertical band-to-band tunneling and is thereby less sensitive to the junction abruptness. The work presents a device and materials platform for exploring III–V tunnel transistors.

Bsim4 and Mosfet Modeling for IC Simulation

Abstract: This book presents the art of advanced MOSFET modeling for integrated circuit simulation and design. It provides the essential mathematical and physical analyses of all the electrical, mechanical and thermal effects in MOS transistors relevant to the operation of integrated circuits. Particular emphasis is placed on how the BSIM model evolved into the first ever industry standard SPICE MOSFET model for circuit simulation and CMOS technology development. The discussion covers the theory and methodology of how a MOSFET model, or semiconductor device models in general, can be implemented to be robust and efficient, turning device physics theory into a production-worthy SPICE simulation model. Special attention is paid to MOSFET characterization and model parameter extraction methodologies, making the book particularly useful for those interested or already engaged in work in the areas of semiconductor devices, compact modeling for SPICE simulation, and integrated circuit design.

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

Abstract: In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I–V and C–V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.

Nearly defect-free Ge gate-all-around FETs on Si substrates

Abstract: The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W fin ) of 52nm and L g of 183nm has I on /I off =105, SS= 130mV/dec, and I on =235 µA/µm at −1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D it =2×1012 cm−2eV−1 is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W eff ) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.

Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm

Abstract: Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [ L g ] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current ( I ON) ) > 100 μA/μm with I ON /I OFF > 10 5 at a drain bias of −1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

Abstract: In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Bifacial CIGS (11% efficiency)/Si solar cells by Cd-free and sodium-free green process integrated with CIGS TFTs

Abstract: CuInGaSe 2 (CIGS) thin-film has successfully grown at low temperature 400 °C for bifacial solar cells and TFTs without degrading the silicon solar cell on the other side. The efficiency of CIGS solar cells reached 6.3% and 11% at 400 and 500 °C, respectively, by sodium-free and Cd-free (n-type ZnS buffer layer used) green technologies. Texturing technique has been introduced here on Si not only to relieve the sodium-free impact on CIGS-crystallization but also to enhance the adhesion between CIGS solar cells and underneath substrate. CIGS TFTs are reported first time and revealed a record-high hole-mobility of 0.22 cm2/V-s. Hybrid CIGS solar cells/TFTs are uniformly formed on 6″ wafers, simultaneously powered with silicon solar cells.

Tunnel FET-based pass-transistor logic for ultra-low-power applications

Abstract: Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm L G . For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.

New sub-20nm transistors: why and how

Abstract: Two new MOSFET structures are candidates for sub-20nm IC technologies according to International Technology Roadmap for Semiconductors. FinFET and UTB-SOI transistors are poised to replace today' s MOSFETs and will provide much needed relief to ICs from their power and device variation predicaments.

Compact models for sub-22nm MOSFETs

Abstract: FinFET and UTBSOI (or ETSOI) FET are the two promising multi-gate FET candidates for sub-22nm CMOS technology. The BSIM-CMG and BSIM-IMG are the surface potential based physical compact models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Both models have been verified by simulation /measurements and show excellent results for all types of real device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

Abstract: This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CGD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.

Denser and more stable FinFET SRAM using multiple fin heights

Abstract: Stability and integration density are two important SRAM performance metrics A well designed SRAM cell has high stability and high integration density Stability and integration density are competing parameters Increasing the stability usually requires increasing the width of the access (AC) transistor, which decreases the integration density SRAM occupies a high percentage of chip area in modern-day chips Any method to decrease the cell area increases the integration density of the chip, and potentially decreases the cost Traditional scaling relied on decreasing the device dimensions by 07× to decrease the area by 05× In the recent times, as the gate length (L G ) scaling slowed down, techniques like thin-cell layouts and Self-Aligned Contacts (SAC) are used to maintain the area scaling trend [1] We propose an SRAM cell with Selectively-Recessed Shallow-Trench Isolation (SR-STI) FinFET to improve the stability and decrease cell area

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

Abstract: For more than 45 years, photon- and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 μm2), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic Vdd regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.

An exercise of ET/UTBB SOI CMOS modeling and simulation with BSIM-IMG

Abstract: This paper presents an exploratory application of BSIM-IMG (May/2011-release) to ET/UTBB SOI MOSFET modeling and circuit simulations. Compliance with fundamental compact model requirements and physical scalability with respect to technology parameters in BSIM-IMG are analyzed. BSIM-IMG model parameters are extracted on a 20nm technology. Simulation results are presented both for conventional benchmark and ET/UTBB SOI specific circuits.

BSIM-CG: A compact model of cylindrical gate / nanowire MOSFETs for circuit simulations

Abstract: A full-fledged surface potential based compact model for cylindrical gate transistors replete with physical effects such as polysilicon gate depletion, mobility degradation, quantum mechanical effects, short channel effects, leakage currents, and parasitic resistances and capacitances etc. is presented. For the first time we present calibration results of such a model to a cylindrical gate technology that exhibits asymmetric i-v characteristics.

User verify and disturb mechanisms in a 65nm flash FPGA

Abstract: We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process Two disturb mechanisms are studied in detail The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability The effect of single and multiple positive charges is simulated It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx 0001 failures per 109 hours per million gates when applied over a 20 year lifetime The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks

A novel bottom-up Ag contact (30nm diameter and 6.5 aspect ratio) technology by electroplating for 1Xnm and beyond technology

Abstract: Very high 6.5 aspect ratio, 30nm diameter contacts are filled with a novel bottom-up Ag electroplating technology for the first time. The technology utilizes two distinct advantages of Ag over Cu: (1) Ag has the lower metal resistivity, and (2) Ag has several orders of magnitude lower diffusivity in Si than Cu. The bottom-up deposition technology intrinsically avoids the issue of seam formation arising from sidewall deposition, and thus is very promising” for future scaled contacts, even down to single digit nano-meter technology nodes.

Silicide barrier engineering induced random telegraph noise in 1Xnm CMOS contacts

Abstract: For the first time, new random telegraph noise behaviors are reported for silicide band gap engineering in advanced nano CMOS technology. Noise current pulses of up to 40% magnitude are observed when Schottky barrier is reduced to 0.2eV. The large contact resistance instability is attributed to barrier modification at Schottky contact interface by positive charge trapping. The prevalence and magnitude of the noise are dependent on the contact size, trap density, trap energy and the silicide Schottky barrier height. In this work, we report a fast monitor methodology to identify the silicide process induced traps in small silicide contacts for 1Xnm CMOS technology.