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Proceedings ArticleDOI

Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation

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TLDR
In this paper, a design methodology of ferroelectric (FE) negative capacitance FETs based on the concept of capacitance matching is presented, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the oncurrent in exchange for a nominal hysteresis.
Abstract
A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET operation, called the “antiferroelectric mode” is proposed, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the on-current in exchange for a nominal hysteresis. Design considerations for different device parameters (FE thickness, EOT, source/drain overlap & gate length) are explored. It is suggested that relative improvement in device performance due to FE negative capacitance becomes more significant in very short channel length devices because of the increased drain-to-channel coupling.

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Journal ArticleDOI

Two-dimensional materials for next-generation computing technologies.

TL;DR: The opportunities, progress and challenges of integrating two-dimensional materials with in-memory computing and transistor-based computing technologies, from the perspective of matrix and logic computing, are discussed.
Journal ArticleDOI

Sustained Sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors

TL;DR: Remarkable sub-60 mV/dec switching was obtained from 2D NC-FETs of various sizes and gate stack thicknesses, demonstrating great potential for enabling size- and voltage-scalable transistors.
Journal ArticleDOI

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

TL;DR: It is shown that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower subthreshold swing and supply voltage in field-effect transistors.
Journal ArticleDOI

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

TL;DR: In this paper, the authors report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs with gate length $L_{g}=100$ nm.
Journal ArticleDOI

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

TL;DR: In this paper, the authors demonstrate a nearly hysteresis-free sub-60mV/decade subthreshold swing operation in a p-type bulk metaloxide-semiconductor field effect transistor externally connected to a ferroelectric capacitor.
References
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Journal ArticleDOI

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI

Crystalline Oxides on Silicon: The First Five Monolayers

TL;DR: In this paper, a metaloxide-semiconductor capacitor using SrTiO{sub 3} as an alternative to SiOthinsp{sub 2} yields the extraordinary result of t{sub eqlt}10 {Angstrom}.
Journal ArticleDOI

Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures

TL;DR: In this article, a proof-of-concept demonstration of negative capacitance effect in a nanoscale ferroelectric-dielectric heterostructure was presented. But the authors did not consider the effect of temperature on the performance of a bilayer of Pb(Zr0.2Ti0.8)O3 and dielectric SrTiO3.
Journal ArticleDOI

Commercial molecular beam epitaxy production of high quality SrTiO3 on large diameter Si substrates

TL;DR: In this article, a molecular beam epitaxy production process for the epitaxial growth of high quality, single crystal, single phase SrTiO3 (STO) films on Si substrates with diameter up to 8in.
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