Showing papers by "Chenming Hu published in 2017"

Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf 0.8 Zr 0.2 O 2 , High Endurance and Breakdown Recovery

Abstract: We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics

Abstract: In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters.

Stabilization of ferroelectric phase in tungsten capped Hf0.8Zr0.2O2

Abstract: We report on the stabilization of the ferroelectric phase in Hf0.8Zr0.2O2 with a tungsten capping layer. Ferroelectricity is obtained in both metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors with highly-doped Si serving as the bottom electrode in the MIS structure. Ferroelectricity is confirmed from both the electrical polarization-voltage (P-V) measurement and X-Ray Diffraction analysis that shows the presence of an orthorhombic phase. High-resolution Transmission Electron Microscopy and Energy Dispersive X-ray spectroscopy show minimal diffusion of W into the underlying Hf0.8Zr0.2O2 after the crystallization anneal. This is in contrast to significant Ti and N diffusion observed in ferroelectric HfxZr1-xO2 commonly capped with TiN.

FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

Abstract: We experimentally demonstrate n-channel bulk FinFET with encased air-gap spacers. Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing them with silicon nitride (SiN) film and finally removing carbon using mild oxygen plasma. We show that the drive current of air-spacer FinFET is improved by about 40% compared with the baseline bulk FinFET with SiN spacers likely due to enhanced tensile stress in the channel. The parasitic capacitance and ring oscillator delay of FinFET with air-spacers is about 25% and 40% lower compared with that with SiN spacers.

Differential voltage amplification from ferroelectric negative capacitance

Abstract: We demonstrate that a ferroelectric can cause a differential amplification without needing such an external energy source. As the ferroelectric switches from one polarization state to the other, a transfer of energy takes place from the ferroelectric to the dielectric, determined by the ratio of their capacitances, which, in turn, leads to the differential amplification. This amplification is very different in nature from conventional inductor-capacitor based circuits where an oscillatory amplification can be observed. The demonstration of differential voltage amplification from completely passive capacitor elements only has fundamental ramifications for next generation electronics.

A Predictive Tunnel FET Compact Model With Atomistic Simulation Validation

Abstract: A predictive tunnel FET compact model is proposed. Gaussian quadrature method is used to overcome the challenge of integration. This provides the flexibility to use Wentzel–Kramers–Brillouin under spatially varying electric field, to incorporate effective band edge states broadening, and to evaluate the drain current by Landauer equation with consideration of electron reflection at the tunnel junction. The model not only shows good accuracy, speed, and smoothness, but is also some predictive capability so that the effects of changing material parameters on IC characteristics are well captured. The model is validated with atomistic simulation data for several materials.

Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling

Abstract: We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high- $ {\kappa } $ , silicon nitride/silicon dioxide dual- $ {\kappa } $ , and silicon dioxide (SiO2) low- $ {\kappa } $ spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low- $\kappa $ spacer FinFET is better due to lower parasitic capacitance ( ${C}_{\mathrm {par}}$ ). We show that ${C} _{\mathrm {par}}$ in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of ${C} _{\mathrm {par}}$ compared with the intrinsic capacitance ( ${C} _{\mathrm {ox}}$ ) increases. For FinFET with Si3N4 spacers, ${C} _{\mathrm {par}}/{C} _{\mathrm {ox}}$ increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively.

Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

Abstract: The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wf m ) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%∼29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

Full chip power benefits with negative capacitance FETs

Abstract: We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

Abstract: Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This problem is exacerbated with the introduction of multigate FETs such as FinFET and gate-all-around FETs. In this paper, we introduce the corner spacer design for gate-all-around nanowire FET to significantly decrease parasitic capacitance with negligible degradation in ON-current. We show that the parasitic capacitance of a well-engineered corner spacer in a nanowire FET can be reduced by over 80% compared to the device with full nitride spacers. Ring oscillator stage delay and energy consumption of the corner spacer design are lower than the full spacer by over 50% each. This paper shows the possibility of engineering the spacers as a performance booster to continue scaling.

Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

Abstract: We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data.

Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling

Abstract: In this paper, we report anomalous behavior of transconductance ( ${g}_{m}$ ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The ${g}_{m}$ characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the ${g}_{m}$ behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical ${g}_{m}$ behavior. The effect of oxide thickness ( ${T}_{\text {ox}}$ ) variation on ${g}_{m}$ is also studied, which demonstrates a deviation from the conventional $g_{m}$ behavior for halo implanted devices with thicker ${T}_{\text {ox}}$ . A computationally efficient SPICE model is proposed to model ${g}_{m}$ characteristics which shows excellent matching with the measured data.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

Abstract: The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

Ferroelectricity in HfO 2 thin films as a function of Zr doping

Abstract: We have studied the effect of Zr doping, from 0% to 100%, on the ferroelectric properties of HfO 2 . Amorphous Hf x Zr 1−x O 2 on TiN and Si substrates is deposited using atomic layer deposition (ALD) and then annealed in a rapid thermal processing (RTP) tool while capped by 20 nm of sputtered TiN. Based on our experiments, Zr doping of up to 50% results in ferroelectricity in polycrystalline Hf x Zr 1−x O 2 , whereas Zr doping of 70% and above shows antiferroelectricity. Our results show how the properties of ferroelectric HfO 2 can be engineered through changing doping and annealing conditions, thereby demonstrating the flexibility of ferroelectric HfO 2 for integration in future memory and logic devices.

High V th enhancement mode GaN power devices with high I D, max using hybrid ferroelectric charge trap gate stack

Abstract: In this work, we demonstrate a new concept for realizing high threshold voltage (V th ) E-mode GaN power devices with high maximum drain current (I D, max ). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of V th . The E-mode GaN MIS-HEMTs with high V th of 6 V shows I D, max 720 mA/mm. The breakdown voltage is above 1100 V.

High-gain monolithic 3D CMOS inverter using layered semiconductors

Abstract: We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Abstract: In this paper, we present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-V TH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of V DS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (L eff) and channel doping (N SUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

Investigation of Mo/Ti/AlN/HfO 2 High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application

Abstract: Use of the Mo/Ti/AlN/HfO2 metal/dielectric stack to increase the permittivity of HfO2 for low power consumption InGaAs-based MOSFET is investigated in this letter. The dielectric constant of HfO2 was found to increase by 47%, from 17 to 25, after Ti doping without affecting the interface trap density around the mid-gap of the MOSCAPs. A strong inversion behavior with low leakage current for the MOSCAP was also observed. The gate voltage needed to tune the Fermi level of InGaAs channel was found to be smaller for the Ti-doped HfO2 sample as compared with the sample with un-doped HfO2. The increase of the dielectric constant of HfO2 after Ti doping combined with the use of Ti gate metal, which has the work function level near the conduction band edge of InGaAs, makes the proposed Mo/Ti/HfO2 (Ti) stack ideal for future lowpower consumption InGaAs-based NMOS applications.

Analysis and modeling of capacitances in halo-implanted MOSFETs

Abstract: In this paper, we report the anomalous behavior of capacitances in halo channel MOSFET for the linear and saturation regions. Unlike MOSFETs these devices have different threshold voltage (V TH ) for the DC and CV operations, and therefore cannot be modeled by conventional methods. We have investigated various cases of doping non-uniformity: Source side halo (SH), Drain side halo (DH), both side halos (Halo) and uniformly doped (UD) transistors using TCAD simulations under various bias conditions. A computationally efficient SPICE model is used to model these trends which shows excellent matching with the measured and TCAD data.

Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs

Abstract: In this paper we present a model to capture the effect of the body-bias on the overlap capacitances. The main hurdle while introducing body-bias dependence in gate-source and gate-drain overlap capacitances is maintaining reciprocity for all capacitances. We propose a subcircuit approach to help maintain reciprocity while including body-bias dependence in overlap charges. The approach is generic, and works for any device. The model has been implemented in BSIM6 industry standard model and has been validated with TCAD simulations as well as experimental measurements.

Differential voltage amplification from ferroelectric negative capacitance

Abstract: It is well known that one needs an external source of energy to provide voltage amplification. Because of this, conventional circuit elements such as resistors, inductors or capacitors cannot provide amplification all by themselves. Here, we demonstrate that a ferroelectric can cause a differential amplification without needing such an external energy source. As the ferroelectric switches from one polarization state to the other, a transfer of energy takes place from the ferroelectric to the dielectric, determined by the ratio of their capacitances, which, in turn, leads to the differential amplification. {This amplification is very different in nature from conventional inductor-capacitor based circuits where an oscillatory amplification can be observed. The demonstration of differential voltage amplification from completely passive capacitor elements only, has fundamental ramifications for next generation electronics.

Stressor design for FinFETs with air-gap spacers

Abstract: The impact of various stressor elements on the performance of n-channel FinFET is summarized. Experimental FinFETs with air-gap spacer shows 25% drive current improvement despite slightly larger series resistance. TCAD suggests that carbon incorporation into the fin is the most likely explanation for drive current increase.

Impact of Al content on InAs/AlSb/Al x Ga 1− x Sb tunnelling diode

Abstract: A method to engineer the peak-to-valley ratio (PVR) by design of the epitaxial layers is presented. The impact of Al content on PVR of InAs/AlSb/Al x Ga1−x Sb tunnelling diode is studied. A simplified analytical model is used to explain the PVRs dependence on Al content. It was found that PVR reaches its maximum when Al content x is zero with a quantised InAs layer. The peak positions appeared in the negative differential region are effectively controlled by the applied gate bias. A PVR ratio as high as 7.1 was achieved, which is beneficial for a wide range of circuit applications. Adjusting Al content provides a new way to engineer the PVR as opposed to the conventional way of being optimised by varying barrier thicknesses or doping levels.