Proceedings ArticleDOI
Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
Jerome Mitard,B. De Jaeger,Frederik Leys,Geert Hellings,Koen Martens,Geert Eneman,David P. Brunco,Roger Loo,Jing-Cheng Lin,Denis Shamiryan,T. Vandeweyer,Gillis Winderickx,E. Vrancken,C.H. Yu,K. De Meyer,Matty Caymax,Luigi Pantisano,Marc Meuris,M.M. Heyns +18 more
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TLDR
In this paper, a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA /mum @Vdd= -1V.Abstract:
We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.read more
Citations
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Journal ArticleDOI
Considerations for Ultimate CMOS Scaling
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Journal ArticleDOI
Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Journal ArticleDOI
Germanium Based Field-Effect Transistors: Challenges and Opportunities
Patrick S. Goley,Mantu K. Hudait +1 more
TL;DR: This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack.
Journal ArticleDOI
Correlated Electron Materials and Field Effect Transistors for Logic: A Review
You Zhou,Shriram Ramanathan +1 more
TL;DR: In this article, a review of metal-insulator transition mechanisms in correlated electron materials and three-terminal field effect devices utilizing such correlated oxides as the channel layer is presented.
Journal ArticleDOI
GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current
Louis Hutin,C. Le Royer,J.-F. Damlencourt,J.M. Hartmann,H. Grampeix,V. Mazzocchi,Claude Tabone,Bernard Previtali,A. Pouydebasque,Maud Vinet,O. Faynot +10 more
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).
References
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Journal ArticleDOI
Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates
B. De Jaeger,Renaud Bonzom,Frederik Leys,O. Richard,J. Van Steenbergen,Gillis Winderickx,E. Van Moorhem,G. Raskin,Fabrice Letertre,T. Billon,Marc Meuris,M.M. Heyns +11 more
TL;DR: In this article, a thin epitaxially grown Si layer is used as the high-k dielectric to obtain low interface state density and high carrier mobility for Ge MOSFETs.