Veena Misra

Abstract: A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.

TL;DR: In this article, the authors extended constraint theory to crystalline silicon-dielectric interfaces that go beyond Si-SiO2 through development of a model that quantifies average bonding coordination at these interfaces.

TL;DR: The latest advances in high-efficiency nanostructured energy harvesters and storage capacitors, new sensing modalities that consume less power, low power computation, and communication strategies, and novel flexible materials that provide form, function, and comfort are presented.

TL;DR: In this paper, an anodized metal oxide (AAO) thin film is used as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template.

TL;DR: The preliminary efforts to achieve a submilliwatt system ultimately powered by the energy harvested from thermal radiation and motion of the body are described with the primary contributions being an ultralow-power ozone sensor, an volatile organic compounds sensor, spirometer, and the integration of these and other sensors in a multimodal sensing platform.