Clevenger Leigh Anne H

TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.

TL;DR: In this article, the authors demonstrate that the formation temperature of the C54 TiSi2 phase from the bilayer reaction of Ti on Si is lowered by placing an interfacial layer of Mo or W between Ti and Si.

TL;DR: In this article, the authors demonstrate the use of a synchrotron radiation source for in situ x-ray diffraction analysis during rapid thermal annealing (RTA) of 0.35 μm Salicide and 0.4 μm Polycide (silicided polysilicon) TiSi2 Complementary Metal Oxide Semiconductor (CMOS) gate structures.

TL;DR: In this article, a 32 nm BEOL with PVD CuMn seedlayer and conventional PVD-TaN/Ta liner was fully characterized by fundamental, integrated, and reliability methods.

TL;DR: In this article, a fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node, where select chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics.