C
Chengwen Pei
Researcher at IBM
Publications - 53
Citations - 648
Chengwen Pei is an academic researcher from IBM. The author has contributed to research in topics: Trench & Layer (electronics). The author has an hindex of 15, co-authored 53 publications receiving 627 citations. Previous affiliations of Chengwen Pei include GlobalFoundries.
Papers
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Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Patent
Integrated circuit with finfets and mim fin capacitor
TL;DR: In this paper, an integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. And a method includes forming a first fin FET comprising a first dielectric and a first conductor.
Patent
Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode
TL;DR: In this article, a shallow trench isolation structure is formed in the semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill.
Proceedings ArticleDOI
A 0.127 μm 2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications
Geng Wang,Kangguo Cheng,Herbert L. Ho,J. Faltermeier,W. Kong,Hyun-Chul Kim,J. Cai,C. Tanner,Kevin McStay,K. Balasubramanyam,Chengwen Pei,Lisa Y. Danbury Ninomiya,Xiaolin Li,Kevin R. Winstel,David M. Dobuzinsky,Munir-ud-Din Naeem,R. Zhang,R. Deschner,MaryJane Brodsky,Scott D. Allen,J. Yates,Y. Feng,P. Marchetti,C. Norris,D. Casarotto,John Benedict,A. Kniffm,D. Parise,Babar A. Khan,J. Barth,Paul C. Parries,T. Kirihata,James P. Norum,S.S. Iyer +33 more
TL;DR: In this paper, a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL).
Patent
Electrical fuse having a thin fuselink
TL;DR: In this article, a thin metal semiconductor alloy fuselink has been used for electrical fuses with a smaller cross-sectional area compared with prior-art electrical fusions.