Institution
Finisar
Company•Sunnyvale, California, United States•
About: Finisar is a company organization based out in Sunnyvale, California, United States. It is known for research contribution in the topics: Signal & Laser. The organization has 900 authors who have published 1523 publications receiving 22634 citations.
Papers published on a yearly basis
Papers
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12 Aug 2003TL;DR: In this paper, an adapter element is provided for interfacing with a card guide of a card cage system to enable ready definition of various card storage configurations within the card cage systems.
Abstract: An adapter element is provided for interfacing with a card guide of a card cage system to enable ready definition of various card storage configurations within the card cage system The adapter element is configured to be removably attached to a card guide so that different card storage configurations may be readily defined within a particular card storage level by removing one or more adapter elements from the corresponding card guides and/or positioning one or more adapter elements in corresponding card guides Additionally, the adapter element is configured to engage the fasteners of a functional module so as to securely retain the functional module in position in the card cage assembly when the adapter element is attached to the card guide
35 citations
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30 May 2003TL;DR: In this paper, the authors propose a modification subsystem suitable for introducing user-defined errors into a designated data unit substantially in real time, so as to facilitate evaluation of the response of a high speed data communications system to errors as such are exemplified in the modified data unit.
Abstract: A modification subsystem suitable for introducing user-defined errors into a designated data unit substantially in real time, so as to facilitate evaluation of the response of a high speed data communications system to errors as such are exemplified in the modified data unit. The modification subsystem includes a modification logic and state machine that communicates with a command stack memory and one or more jamming mode registers. Upon locating and identifying the designated data unit in a data stream, the modification logic and state machine accesses a jam setting stored in a jam mode register and, if it is determined that the modification that corresponds to the jam setting is valid, modifies the designated data unit in accordance with the jam setting. If the proposed modification is invalid, the modification is aborted.
35 citations
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28 Dec 2001TL;DR: An integral vertical cavity surface emitting laser (VCSEL) and power monitor assembly is proposed in this article, where the assembly is beneficially fabricated by anisotropic etching a silicon substrate having substantially flat top and bottom surfaces to form a cavity (136) defined by an inwardly sloping wall that extends through the silicon substrate, beneficially to a membrane.
Abstract: An integral vertical cavity surface emitting laser (VCSEL) and power monitor assembly. The assembly is beneficially fabricated by anisotropically etching a silicon substrate (118) having substantially flat top and bottom surfaces to form a cavity (136) defined by an inwardly sloping wall that extends through the silicon substrate, beneficially to a membrane. A photodetector (116) (light sensor) is formed adjacent the cavity (such as on a membrane), and a VCSEL (112) is attached to the silicon substrate such that light (114) from the VCSEL irradiates the photodetector. Beneficially, the photodetector is a metal-semiconductor-metal photodetector. An optical element (138) (a lens) and the end of an optical fiber (140) are beneficially located in the cavity. The optical element couples light that passes through the photodetector into the optical fiber.
35 citations
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29 May 1998TL;DR: In this paper, a common clock is located on a network analyzer device which acts as the master to other "slave" peripheral network devices which are driven by the common clock and coupled to the master device in a master-slave configuration.
Abstract: A system for synchronizing data packet collection and transmission on multiple segments of a local area network (“LAN”) or a wide area network (“WAN”) using a common clock to generate time stamps placed on the data packets by all peripheral network devices. The common clock is located on a network analyzer device which acts as the “master” to other “slave” peripheral network devices which are driven by the common clock and coupled to the master device in a master-slave configuration. The system also synchronizes the initialization of data packet transmission and/or collection on multiple peripheral network devices by using a common industry standard architecture (“ISA”) address for all devices involved in the data transmission and/or collection.
35 citations
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28 Feb 2008TL;DR: In this paper, the authors propose a multi-mode serializer with a dual-mode bypass block for allowing data signals to go straight from input nodes to a multiplexing block or decoding encoded data signals.
Abstract: A multi-mode SerDes may be implemented in at least two different optoelectronic device architectures. The serializer includes a dual-mode bypass block for allowing data signals to go straight from input nodes to a multiplexing block or for decoding encoded data signals. A final dynamic high speed multiplexer multiplexes two data signals into one serial signal, or allows a single signal to go through. The deserializer includes an input dynamic high speed demultiplexer for demultiplexing one serial signal into two, or for allowing a serial signal through. A dual-mode bypass block is provided to allow data signals to go straight through from a demultiplexing block to output nodes or to encode data signals prior to providing them to the output nodes.
35 citations
Authors
Showing all 900 results
Name | H-index | Papers | Citations |
---|---|---|---|
Yaron Silberberg | 87 | 462 | 28905 |
Ray T. Chen | 54 | 889 | 12078 |
Naresh R. Shanbhag | 49 | 325 | 9202 |
N.A. Olsson | 38 | 158 | 6360 |
Andrew C. Singer | 38 | 302 | 6721 |
Jae-Hyun Ryou | 35 | 260 | 5038 |
Joyce K. S. Poon | 33 | 156 | 4184 |
Yasuhiro Matsui | 31 | 143 | 2844 |
Ying Luo | 30 | 105 | 2992 |
Lewis B. Aronson | 29 | 74 | 2251 |
Thomas W. Mossberg | 29 | 131 | 2611 |
Daniel Mahgerefteh | 25 | 88 | 1830 |
Gil Cohen | 25 | 72 | 2564 |
Christoph M. Greiner | 24 | 100 | 1423 |
James A. Cox | 23 | 72 | 1718 |