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Institution

Finisar

CompanySunnyvale, California, United States
About: Finisar is a company organization based out in Sunnyvale, California, United States. It is known for research contribution in the topics: Signal & Laser. The organization has 900 authors who have published 1523 publications receiving 22634 citations.


Papers
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Patent
Gayle L. Noble1
04 May 2007
TL;DR: A network diagnostic system may include a statistics module as discussed by the authors, which is used to add and remove entries to a data structure, and to help maintain one or more network diagnostic statistics.
Abstract: A network diagnostic system may include a statistics module. The statistics module may include a plurality of stages and may include stage-transition code. The stage-transition code may be used to help maintain one or more network diagnostic statistics. The statistics module may be implemented using a network processor unit, and the network processor unit may include a plurality of stages and may include stage-transition code. To help maintain one or more network diagnostic statistics, the statistics module may add and remove entries to a data structure.

6 citations

Patent
09 Aug 2013
TL;DR: In this article, an example embodiment includes a communication module including a shell, a printed circuit board assembly ("PCBA") at least partially positioned within the shell, an optical transmitter and an optical receiver electrically coupled to the PCBA, and a biasing assembly.
Abstract: An example embodiment includes a communication module. The communication module includes a shell, a printed circuit board assembly ("PCBA") at least partially positioned within the shell, an optical transmitter electrically coupled to the PCBA, an optical receiver electrically coupled to the PCBA, and a biasing assembly. The biasing assembly includes a latch cover configured to be attached to the shell, a slider, and a spring. The slider is configured to operate a latching mechanism that releasably connects the module to a host device through a mechanical connection. The slider includes a main body including a first end, an arm extending from the first end, and a stopper feature extending from the arm. The spring is positioned between the latch cover and the stopper feature to bias the latching mechanism.

6 citations

Journal ArticleDOI
TL;DR: In this paper, the NBTI/PBTI reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature.
Abstract: In this work, negative bias temperature instability/positive bias temperature instability (NBTI/PBTI) reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature. We have incorporated the NBTI/PBTI $\text{V}_{\mathrm{ T}}$ model in a physics-based SiNW FET Verilog-A compact model for circuit analysis. For the first time, using integrated model, we report time zero variability and BTI reliability of the core logic gates (INVERTER, NAND, and NOR) and read/write stability of 6T SRAM cell. We demonstrate that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. The benchmarking of BTI in SiNW FET with FinFET and planar devices show SiNW have higher degradation, however it can be minimized by using optimized SiNW FET configuration. Further, we show that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the read noise margin (RNM) by 15–30%, and write noise margin (WNM) improves by 5–8% for 10-Year lifetime. We find that the combined impact of time zero variability and BTI reliability degrades the mean value of circuit delay and SRAM RNM stability, however, the degradation is found to be comparable to the reported planar and FinFET data. It is also seen that different configuration increases BTI variability (~5-25% increase) which can be minimized. Using the results, we propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate SiNW FET design configuration. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis.

6 citations

Patent
26 Aug 2004
TL;DR: In this paper, a waveguide layer is configured to expand the optical mode into the layers beneath the active region, which enables the thickness of the layers above the active regions to be reduced, thereby reducing leakage current.
Abstract: Systems and methods for expanding an optical mode of a laser or optical amplifier to reduce leakage current. A waveguide layer is included in a laser that optically couples with the active region. The waveguide layer is configured to expand the optical mode into the layers beneath the active region. This enables the thickness of the layers above the active region to be reduced, thereby reducing leakage current. Because the waveguide layer expanded the optical mode without substantially reducing the optical confinement of the active region, the optical loss associated with the metal contact is also reduced even though the layers between the active region and the metal contact have been thinned. In one embodiment, the threshold current is reduced.

6 citations

Patent
30 Jun 2005
TL;DR: In this paper, a method for an optical transceiver (or transmitter or receiver) to change from a first set of functionality to a second set of functionalities that are different than the first set is presented.
Abstract: A method for an optical transceiver (100) (or transmitter or receiver) to change from a first set of functionality to a second set of functionality that is different than the first set of functionality. The optical transceiver has at least one processor (203) and a system memory (206). The optical transceiver has access to a persistent memory (106). The persistent memory includes microcode (121) that when loaded into system memory and executed by the processor, causes the optical transceiver to have access to a first set of functionality. In order to implement the method, second microcode (122) in the persistent memory is made accessible to the optical transceiver. The second microcode includes one or more functions in the second set of functionality that are not included in the first set of functionality. Then, the second microcode is loaded in the system memory from the persistent memory and executed to implement the second set of functionality.

6 citations


Authors

Showing all 900 results

NameH-indexPapersCitations
Yaron Silberberg8746228905
Ray T. Chen5488912078
Naresh R. Shanbhag493259202
N.A. Olsson381586360
Andrew C. Singer383026721
Jae-Hyun Ryou352605038
Joyce K. S. Poon331564184
Yasuhiro Matsui311432844
Ying Luo301052992
Lewis B. Aronson29742251
Thomas W. Mossberg291312611
Daniel Mahgerefteh25881830
Gil Cohen25722564
Christoph M. Greiner241001423
James A. Cox23721718
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20221
20213
202019
201929
201821
201743