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Journal ArticleDOI

3-D Analytical Modeling of Dual-Material Triple-Gate Silicon-on-Nothing MOSFET

Pritha Banerjee, +1 more
- 20 Jan 2017 - 
- Vol. 64, Iss: 2, pp 368-375
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TLDR
In this paper, a 3D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET, was proposed, and the surface potential variation of the structure considering the popular parabolic potential approximation was calculated.
Abstract
A 3-D analytical model of a new structure, namely, dual-material triple-gate silicon-on-nothing MOSFET is proposed in this paper. 3-D Poisson’s equation with proper boundary conditions was solved to obtain the surface potential variation of the structure considering the popular parabolic potential approximation, and the threshold voltage and electric field were calculated for the model. The proposed model’s immunity to the various short-channel effects, such as threshold voltage roll-off, Drain-Induced Barrier Lowering (DIBL), and subthreshold swing, are also examined, and the impact of the various device parameters on the performance of the device is studied. The 3-D simulated results obtained using ATLAS, a device simulator from Silvaco, validate the analytical results obtained for this structure.

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Citations
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2D analytical modeling and simulation of dual material DG MOSFET for biosensing application

TL;DR: In this article, an analytical model of the double gate (DG) MOSFET was presented and the threshold voltage was determined by solving the 2-D Poisson's equation using a parabolic potential approach.
Journal ArticleDOI

3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

TL;DR: In this paper, a detailed study of the response of a high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate towards various short channel effects, namely, drain-induced barrier lowering, threshold voltage roll-off, hot carrier effect and subthreshold swing, is presented.
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3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor

TL;DR: In this paper, a dual material tri-gate (DM TG) tunnelling field effect transistor (TFET) obtained by intermixing the c... is presented in a detailed three-dimensional analytical modelling and simulation study.
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Analytical model development of channel potential, electric field, threshold voltage and drain current for gate workfunction engineered short channel E-mode N-polar GaN MOS-HEMT

TL;DR: In this article, an enhancement mode (E-mode) short channel N-polar GaN MOS-HEMT is proposed to mitigate different short channel effects, work function engineering technique is applied to the gate electrode.
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Analytical modeling of a high- K underlap dielectric- and charge-modulated silicon-on-nothing FET-based biosensor

TL;DR: In this article, an underlap silicon-on-nothing FET-based biosensor with high-K gate oxide is presented for the detection of charged biomolecules, thereby removing the unwanted interfacial layer while preserving the sensitivity of the device.
References
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Journal ArticleDOI

Short-channel effect in fully depleted SOI MOSFETs

TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Journal ArticleDOI

Scaling theory for double-gate SOI MOSFET's

TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Journal ArticleDOI

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

TL;DR: In this article, the authors presented the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET.
Posted Content

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

TL;DR: In this paper, the authors presented the unique features exhibited by modified asymmetrical double gate (DG) silicon on insulator (SOI) MOSFET, which exhibits significantly reduced short channel effects.
Journal ArticleDOI

A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

TL;DR: An analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time in this article, which explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation.
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