Proceedings ArticleDOI
A new rail-to-rail ultra low voltage high speed comparator
Masoume Akbari,Mohammad Maymandi-Nejad,S. Abdollah Mirbozorgi +2 more
- pp 1-6
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TLDR
In this paper, a rail-to-rail input high-performance regenerative comparator was proposed for lowvoltage low-power applications, e.g. bio-implantable circuits.Abstract:
This paper presents a new rail-to-rail input highperformance regenerative comparator suitable for low-voltage low-power applications, e.g. bio-implantable circuits. In this circuit the body of the PMOS transistor is used as comparator's input. A technique is proposed to increase the speed of the circuit. The proposed comparator has a good performance in weak inversion (sub-threshold). Simulations are done in the 0.18-μm CMOS technology with a supply voltage of 0.5 V. The propagation delay time of the second proposed comparator is 16.4 ns, the power dissipation is 20 nW and the power delay product is 0.33 fJ in clock frequency of 5 MHz and input voltage of 500 μV. Also the supply voltage can be decreased to 0.3 V.read more
Citations
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A Smart Multicoil Inductively Coupled Array for Wireless Power Transmission
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Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator
TL;DR: A new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area, and it is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator.
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Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator
TL;DR: In this article, a double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator.
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Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples
Viera Stopjakova,Matej Rakus,Martin Kovac,Daniel Arbet,Lukas Nagy,Michal Sovcik,Miroslav Potocny +6 more
TL;DR: In this article, an overview of main challenges and design techniques effectively applicable for ultra-low voltage analog integrated circuits in nanoscale technologies is presented, and the developed circuits are compared to the state-of-the-art solutions in terms of the main parameters and features.
Journal ArticleDOI
An ultra low-voltage rail-to-rail comparator for on-chip energy harvesters
TL;DR: In this paper, the authors present a performance evaluation of an ultra lowvoltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology.
References
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Proceedings ArticleDOI
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Journal ArticleDOI
Yield and speed optimization of a latch-type voltage sense amplifier
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Journal ArticleDOI
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
TL;DR: In this article, two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described, one is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Journal Article
A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture
TL;DR: In this paper, two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described, one is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Journal ArticleDOI
A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V
Bernhard Goll,Horst Zimmermann +1 more
TL;DR: A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.65-V supply.