Proceedings ArticleDOI
A novel TSV model considering nonlinear MOS effect for transient analysis
Kuan-Yu Chen,Yi-An Sheu,Chi-Hsuan Cheng,Jyun-Hong Lin,Yih-Peng Chiou,Tzong-Lin Wu +5 more
- pp 49-52
TLDR
In this paper, a novel equivalent circuit model of through-silicon via (TSV) considering the time-dependent capacitance due to metal-oxide-semiconductor (MOS) effect has been proposed.Abstract:
A novel equivalent circuit model of through-silicon via (TSV) considering the time-dependent capacitance due to metal-oxide-semiconductor (MOS) effect has been proposed. This model can characterize the variance of capacitance between metal and silicon substrate caused by the differential change of depletion region width as the voltage applied on the TSV changes with time. Compared to conventional TSV models, the capacitance has a 70% difference when the TSV's applied voltage transits from low state to high state. Besides, 3% difference of eye height and 100% difference of eye jitter can be observed in eye diagram by SPICE simulation.read more
Citations
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Journal ArticleDOI
Transient Analysis of TSV Equivalent Circuit Considering Nonlinear MOS Capacitance Effects
TL;DR: In this paper, an equivalent circuit model for the transient analysis of through-silicon vias (TSV) taking into account nonlinear metaloxide-semiconductor effects is proposed.
Journal ArticleDOI
An Analytical Through Silicon Via (TSV) Surface Roughness Model Applied to a Millimeter Wave 3-D IC
TL;DR: In this article, the impact of the TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed.
Journal ArticleDOI
Impact of Frequency-Dependent and Nonlinear Parameters on Transient Analysis of Through Silicon Vias Equivalent Circuit
TL;DR: In this paper, an equivalent circuit model for through silicon vias including the nonlinear effect of metaloxide-semiconductor capacitance is introduced, which is combined to the frequency-dependent via resistance and inductance, as well as capacitance and conductance of the silicon substrate for a transient analysis.
Journal ArticleDOI
Role of Through Silicon Via in 3D Integration: Impact on Delay and Power
TL;DR: A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures, and the power delay product (PDP) of the tapered MES is reduced by 92.4%Compared to the conventional MIS-based cylindrical TSV.
Journal ArticleDOI
Equivalent Circuit Modeling of Dielectric Hysteresis Loops in Through Silicon Vias
TL;DR: In this paper, a numerical solution of the nonlinear equations that describe the hysteretic behavior of the coupling capacitance among through silicon vias in three-dimensional integrated circuits is proposed.
References
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Journal ArticleDOI
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
TL;DR: In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics, and a TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures.
Journal ArticleDOI
High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
Joohee Kim,Jun So Pak,Jonghyun Cho,Eakhwan Song,Jeonghyeon Cho,Heegon Kim,Taigon Song,Jun Ho Lee,Hyungdong Lee,Kunwoo Park,Seung-Taek Yang,Min Suk Suh,Kwang-Yoo Byun,Joungho Kim +13 more
TL;DR: In this article, the authors proposed a high-frequency scalable electrical model of a through silicon via (TSV) channel, which includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3D integrated circuit (IC) design.
Journal ArticleDOI
Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs
TL;DR: In this article, the authors presented the first comprehensive and accurate compact RLCG model for through-silicon vias (TSVs) in 3D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon and the skin effect in TSV metal, and the eddy currents in the silicon substrate.
Proceedings ArticleDOI
Electrical modeling of Through Silicon and Package Vias
TL;DR: Analytical modeling and 3D full-wave electromagnetic simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV) and an accurate electrical model of the TSV are presented.
Journal ArticleDOI
Compact Wideband Equivalent-Circuit Model for Electrical Modeling of Through-Silicon Via
TL;DR: In this paper, the authors present a compact wideband equivalent circuit model for electrical modeling of through-silicon vias (TSVs) in 3D stacked integrated circuits and packaging.