Journal ArticleDOI
A study of negative-bias temperature instability of SOI and body-tied FinFETs
TLDR
In this article, negative bias temperature-instability (NBTI) characteristics on SOI and body-tied pMOS FinFETs were investigated for the first time.Abstract:
Negative-bias temperature-instability (NBTI) characteristics are carefully studied on SOI and body-tied pMOS FinFETs for the first time. It was observed that a narrow fin width degraded device lifetime more than a wider fin width. Electrons generated by the NBT stress are accumulated at the center of a silicon fin and cause energy-band bending. This results in an incremental hole population at the interface. The energy band is bent more steeply at the narrow fin than at the wide fin by the accumulated electrons. A body-tied FinFET shows better immunity to NBT stress due to a substrate contact.read more
Citations
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Journal ArticleDOI
Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits
TL;DR: In this article, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated, and the ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL).
Proceedings ArticleDOI
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits
TL;DR: The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.
Proceedings ArticleDOI
Technology scaling on High-K & Metal-Gate FinFET BTI reliability
Kyong Taek Lee,Wonchang Kang,Eun-Ae Chung,Gunrae Kim,Hyewon Shim,Hyun-Woo Lee,Hye-Jin Kim,Minhyeok Choe,Nae-In Lee,Anuj Patel,Junekyun Park,Jongwoo Park +11 more
TL;DR: In this paper, the impact of technology scaling on BTI and BTI on FinFET technology is discussed, where the authors show that BTI degradation is increased while NMOS PBTI was reduced with high-K scaling.
Journal ArticleDOI
Improving bulk FinFET DC performance in comparison to SOI FinFET
TL;DR: In this paper, the authors compared the performance of SOI and bulk FinFET with a three-dimensional numerical device simulator and showed that the latter has equal or better sub-threshold performance than the former.
Journal ArticleDOI
Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs
Cheng-Li Lin,Po-Hsiu Hsiao,Wen-Kuan Yeh,Han-Wen Liu,Syuan-Ren Yang,Yu-Ting Chen,Kun-Ming Chen,Wen-Shiang Liao +7 more
TL;DR: In this paper, the impact of fin width (Wfins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device was investigated.
References
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Journal ArticleDOI
Sub-50 nm P-channel FinFET
Xuejue Huang,Wen-Chin Lee,C. Kuo,Digh Hisamoto,Leland Chang,J. Kedzierski,Erik H. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects, which shows good performance down to a gate-length of 18 nm.
Journal ArticleDOI
Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface.
Shigeo Ogawa,Noboru Shiono +1 more
TL;DR: In this article, a unified phenomenological model of the low-field charge-buildup phenomenon at ultrathin SiO-Si interfaces during negative-bias stresses at elevated temperatures is presented.
Proceedings ArticleDOI
Sub-20 nm CMOS FinFET technologies
Yang-Kyu Choi,Nick Lindert,Peiqi Xuan,S. Tang,Daewon Ha,E. Anderson,T.-J. King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported, which is a more manufacturable process and has less overlap capacitance.
Journal ArticleDOI
Mechanism of negative‐bias‐temperature instability
TL;DR: In this paper, a first-order electrochemical reaction between hydrogenated trivalent silicon, a neutral water-related species located in the oxide near the Si-SiO2 interface, and holes at the silicon surface to form neutral trivalents silicon and a positively charged water−related species is presented.
Proceedings ArticleDOI
NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]
Anand T. Krishnan,Vijay Reddy,Srinivasan Chakravarthi,J. Rodriguez,S. John,Srikanth Krishnan +5 more
TL;DR: In this paper, a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications is described, and the degradation in gate-drain capacitance (C/sub GD/) is quantified for both digital and analog circuits.