Journal ArticleDOI
Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
Christian Enz,Gabor C. Temes +1 more
- Vol. 84, Iss: 11, pp 1584-1614
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TLDR
In this paper, some old and new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain.Abstract:
In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.read more
Citations
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Proceedings ArticleDOI
A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology
TL;DR: In this paper, a two-stage dynamic comparator using offset cancellation technique for the resolution enhancement is proposed, where the offset voltage equations are derived and the mechanism of offset cancellation is analytically explained.
Book ChapterDOI
DeltaSigma A/Ds with Reduced Sensitivity To Op AMP Noise and Gain
James C. Candy,Gabor C. Temes +1 more
TL;DR: New switching schemes which compensate for circuit noise and limited op amp gain are proposed for integrated CMOS switched-capacitor delta-sigma modulators.
Proceedings ArticleDOI
A CMOS closed loop AMR sensor architecture
TL;DR: A fully analog, closed loop, signal conditioning circuit is presented for the readout of Anisotropic MagnetoResistance magnetic sensors, based on a fully differential design based on an instrumentation amplifier with chopping to achieve low output noise.
Proceedings ArticleDOI
Low-noise readout circuit for SWIR focal plane arrays
Oguz Altun,Ferhat Tasdemir,Omer Lutfi Nuzumlali,Reha Kepenek,Ercihan Inceturkmen,Fatih Akyurek,Can Tunca,Mehmet Akbulut +7 more
TL;DR: In this paper, the authors reported a 640x512 SWIR ROIC with 15um pixel pitch that is designed and fabricated using 0.18um CMOS process, where CTIA with single stage amplifier is utilized as input stage.
Proceedings ArticleDOI
Robustness of digital approach to mismatch compensation in analog circuits realized in nanometer technologies
TL;DR: In this article, a fully differential operational transconductance amplifier (OTA) implemented in 65 nm CMOS technology is analyzed to determine which component of the calibration circuitry is most susceptible to manufacturing process disturbances and thus impairs robustness of the OTA calibration methodology.
References
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Book
Principles of Data Conversion System Design
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Journal ArticleDOI
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Proceedings Article
A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Journal ArticleDOI
Design techniques for high-speed, high-resolution comparators
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
MonographDOI
Switched-currents : an analogue technique for digital technology
TL;DR: This book discusses the evolution of Analogue Sampled-Data Signal Processing, the architecture of Switched-Current Circuits, and the non-linear Behaviour of Switches-Current Memory Circuits.