Journal ArticleDOI
Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
Christian Enz,Gabor C. Temes +1 more
- Vol. 84, Iss: 11, pp 1584-1614
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TLDR
In this paper, some old and new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain.Abstract:
In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.read more
Citations
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Patent
Notch filter for ripple reduction in chopper stabilized amplifiers
Rodney T. Burt,Joy Y. Zhang +1 more
TL;DR: In this article, a chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier (2) having an input chopper and an output chopper for chopping an output signal produced by the first operational transceiver.
Proceedings Article
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
TL;DR: In this article, the authors present a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve sub-picosecond jitter performance.
Journal ArticleDOI
Integrated Circuits and Electrode Interfaces for Noninvasive Physiological Monitoring
Sohmyung Ha,Chul Kim,Yu M. Chi,Abraham Akinin,Christoph Maier,Akinori Ueno,Gert Cauwenberghs +6 more
TL;DR: Fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission.
Book
CMOS Analog Design Using All-Region MOSFET Modeling
TL;DR: In this paper, a design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model, is presented, with numerous design examples and exercises also included.
Proceedings Article
A 104-dB dynamic range transimpedance-based CMOS ASIC for tuning fork microgyroscopes
TL;DR: In this article, a T-network transimpedance amplifier (TIA) is used as the front-end for low-noise, sub-atto-Farad capacitive detection.
References
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Book
Principles of Data Conversion System Design
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Journal ArticleDOI
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Proceedings Article
A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Journal ArticleDOI
Design techniques for high-speed, high-resolution comparators
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
MonographDOI
Switched-currents : an analogue technique for digital technology
TL;DR: This book discusses the evolution of Analogue Sampled-Data Signal Processing, the architecture of Switched-Current Circuits, and the non-linear Behaviour of Switches-Current Memory Circuits.