Journal ArticleDOI
Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
Christian Enz,Gabor C. Temes +1 more
- Vol. 84, Iss: 11, pp 1584-1614
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TLDR
In this paper, some old and new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain.Abstract:
In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.read more
Citations
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Journal ArticleDOI
Study of the Influence of Phase Noise on the MEMS Disk Resonator Gyroscope Interface Circuit.
Wenbo Zhang,Weiping Chen,Liang Yin,Xinpeng Di,Dongliang Chen,Qiang Fu,Yufeng Zhang,Xiaowei Liu +7 more
TL;DR: A new time-varying phase noise model for the gyroscope is established, which explains how the drive loop circuit noise converts into phase noise and the impact of phase noise on DRG is derived.
Proceedings ArticleDOI
Compensation of interface circuit errors for MEMS gyroscopes using state observers
TL;DR: In this paper, a state estimation technique was proposed to compensate the errors resulting from interface circuits and mechanical structure uncertainties, and to obtain correct angular rates for MEMS gyroscopes.
Patent
Correlated-double-sampling switched-capacitor gain stages, systems implementing the gain stages, and methods of their operation
TL;DR: In this article, an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state.
Journal ArticleDOI
Accurate modeling of noise in switched-C /spl Delta//spl Sigma/ analog-to-digital converters
Emad Hegazi,N. Klemmer +1 more
TL;DR: An accurate physical model of switched-capacitor /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) noise is presented and design guidelines based on the proposed model are discussed.
Proceedings ArticleDOI
Multi-channel integrated neural interfaces for distributed electro-chemical sensing
J.N.Y. Aziz,Roman Genov +1 more
TL;DR: This work presents two integrated neural interfaces, for chemical and electrical sensing, and performs simultaneous current-mode acquisition of 16 independent channels of redox currents ranging five orders of magnitude in dynamic range over four scales down to hundreds of picoamperes.
References
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Book
Principles of Data Conversion System Design
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Journal ArticleDOI
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Proceedings Article
A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning
Francois Krummenacher,N. Joehl +1 more
TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Journal ArticleDOI
Design techniques for high-speed, high-resolution comparators
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
MonographDOI
Switched-currents : an analogue technique for digital technology
TL;DR: This book discusses the evolution of Analogue Sampled-Data Signal Processing, the architecture of Switched-Current Circuits, and the non-linear Behaviour of Switches-Current Memory Circuits.