Journal ArticleDOI
Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
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TLDR
A new high-speed and low power design of the 3-2 counter and 4-2 compressor of a parallel array multiplier has better speed and power performance than other recently proposed approaches.Abstract:
A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is presented. Owing to the reduction of the internal load capacitance, the counter and compressor have better speed and power performance than other recently proposed approaches.read more
Citations
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Journal ArticleDOI
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Journal ArticleDOI
Low-voltage low-power CMOS full adder
TL;DR: In this paper, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented.
Journal ArticleDOI
Modified Booth Multipliers With a Regular Partial Product Array
TL;DR: A simple approach is proposed to generate a regular partial product array with fewer partial product rows and negligible overhead, thereby lowering the complexity of partial product reduction and reducing the area, delay, and power of MBE multipliers.
Proceedings ArticleDOI
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
TL;DR: Novel architectures and designs of high speed, low power 3-2, 4-2 and 5-2 compressors capable of operating at ultra-low voltages are presented and are shown to perform better.
Journal ArticleDOI
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
TL;DR: Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP.
References
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Journal ArticleDOI
A 54*54-b regularly structured tree multiplier
TL;DR: By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme.
Journal ArticleDOI
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
Vojin G. Oklobdzija,D. Villeger +1 more
TL;DR: Improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile are discussed, yielding a faster multiplier.